Cross Reference: /src/sys/dev/ic/wd33c93.c

Lines Matching refs:csr
293 	u_char	csr, reg;
320 	GET_SBIC_csr(sc, csr);			/* clears interrupt also */
323 	switch (csr) {
882 			int csr;
883 			GET_SBIC_csr(sc, csr);
884 			printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n",
885 			    line, val, csr);
902 	u_char csr, asr;
905 	GET_SBIC_csr(sc, csr);
908 	printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr);
959 				GET_SBIC_csr(sc, csr);
960 				SBIC_DEBUG(MISC, ("csr: 0x%02x, asr: 0x%02x\n",
961 					       csr, asr));
962 			} while ((csr != SBIC_CSR_DISC) &&
963 			    (csr != SBIC_CSR_DISC_1) &&
964 			    (csr != SBIC_CSR_CMD_INVALID));
976  * Returns the current CSR following selection and optionally MSG out phase.
977  * i.e. the returned CSR *should* indicate CMD phase...
985 	u_char target, lun, asr, csr, id;
1032 		GET_SBIC_csr (sc, csr);
1035 		if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) {
1040 			wd33c93_nextstate(sc, acb, csr, asr);
1045 		if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) {
1050 	} while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
1051 		 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
1052 		 csr != SBIC_CSR_SEL_TIMEO);
1055 	if (csr == SBIC_CSR_SEL_TIMEO) {
1090 	if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
1141 		GET_SBIC_csr(sc, csr);
1144 	return csr;
1257 	 * this leaves with one csr to be read
1271 	u_char	phase, csr;
1286 		GET_SBIC_csr (sc, csr);
1287 		QPRINTF(("%02x:", csr));
1288 	} while ((csr != SBIC_CSR_DISC) &&
1289 		 (csr != SBIC_CSR_DISC_1) &&
1290 		 (csr != SBIC_CSR_S_XFERRED));
1313 	u_char			csr, asr;
1338 	if ((csr = wd33c93_selectbus(sc, acb)) == 0)
1346 		QPRINTF(("go[0x%x] ", csr));
1349 		i = wd33c93_nextstate(sc, acb, csr, asr);
1356 				printf("wd33c93_go: LCI asr:%02x csr:%02x\n", asr, csr);
1359 				GET_SBIC_csr(sc, csr);
1380 	u_char	asr, csr;
1389 	GET_SBIC_csr(sc, csr);
1392 		SBIC_DEBUG(INTS, ("intr[csr=0x%x]", csr));
1394 		(void)wd33c93_nextstate(sc, sc->sc_nexus, csr, asr);
1400 				printf("wd33c93_intr: LCI asr:%02x csr:%02x\n",
1401 				    asr, csr);
1404 				GET_SBIC_csr(sc, csr);
1423 	u_char			asr, csr=0;
1431 			printf("wd33c93_poll: LCI; asr:%02x csr:%02x\n",
1432 			    asr, csr);
1434 			GET_SBIC_csr(sc, csr);
1436 			(void)wd33c93_nextstate(sc, sc->sc_nexus, csr, asr);
1475 	u_char asr, csr, *msg;
1482 	GET_SBIC_selid (sc, csr);
1483 	SET_SBIC_selid (sc, csr | SBIC_SID_FROM_SCSI);
1502 		GET_SBIC_csr(sc, csr);
1514 		GET_SBIC_csr(sc, csr);
1527 	/* Should still have one CSR to read */
1892 wd33c93_nextstate(struct wd33c93_softc *sc, struct wd33c93_acb	*acb, u_char csr, u_char asr)
1894 	SBIC_DEBUG(PHASE, ("next[a=%02x,c=%02x]: ",asr,csr));
1896 	switch (csr) {
1947 			printf("next: DATA phase with xfer count == %zd, asr:0x%02x csr:0x%02x\n",
1948 			    acb->dleft, asr, csr);
1963 			if (SBIC_PHASE(csr) == DATA_IN_PHASE)
1975 			int datain = SBIC_PHASE(csr) == DATA_IN_PHASE;
2018 		printf("Acking unknown msgin CSR:%02x",csr);
2078 		if (csr == SBIC_CSR_RSLT_IFY) {
2107 				GET_SBIC_csr(sc,csr);
2109 				if (csr == (SBIC_CSR_MIS   | MESG_IN_PHASE) ||
2110 				    csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) ||
2111 				    csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) {
2124 					printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr);
2136 		if (csr == SBIC_CSR_RSLT_IFY)
2144 		printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr);
2346 wd33c93_print_csr(u_char csr)
2348 	switch (SCSI_PHASE(csr)) {
2374 		switch (csr) {
2400 			printf("UNKNOWN csr=%02x\n", csr);
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