Lines Matching defs:dbch
801 struct fwohci_dbch *dbch;
809 dbch = &sc->ir[dmach];
810 ir = &dbch->xferq;
818 dbch->ndb = ir->bnpacket * ir->bnchunk;
819 dbch->ndesc = 2;
820 fwohci_db_init(sc, dbch);
821 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
823 err = fwohci_rx_enable(sc, dbch);
834 ldesc = dbch->ndesc - 1;
862 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
868 fwdma_sync_multiseg_all(dbch->am,
886 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
915 struct fwohci_dbch *dbch;
921 dbch = &sc->it[dmach];
922 it = &dbch->xferq;
924 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
925 dbch->ndb = it->bnpacket * it->bnchunk;
926 dbch->ndesc = 3;
927 fwohci_db_init(sc, dbch);
928 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
931 err = fwohci_tx_enable(sc, dbch);
936 ldesc = dbch->ndesc - 1;
955 dbch->ndesc;
957 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
958 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
965 fwdma_sync_multiseg_all(dbch->am,
984 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1348 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1360 KASSERT(mutex_owned(&dbch->xferq.q_mtx));
1363 if (dbch->off != OHCI_ATQOFF &&
1364 dbch->off != OHCI_ATSOFF)
1368 if (dbch->flags & FWOHCI_DBCH_FULL)
1371 db_tr = dbch->top;
1373 if (dbch->pdb_tr != NULL) {
1374 kick = dbch->pdb_tr;
1375 fwdma_sync_multiseg(dbch->am, kick->idx, kick->idx,
1379 xfer = STAILQ_FIRST(&dbch->xferq.q);
1383 if (dbch->xferq.queued == 0)
1386 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
1423 if (dbch->off != OHCI_ATSOFF)
1494 if (dbch->pdb_tr != NULL) {
1495 db = LAST_DB(dbch->pdb_tr);
1498 dbch->xferq.queued++;
1499 dbch->pdb_tr = db_tr;
1501 if (db_tr != dbch->bottom)
1505 dbch->flags |= FWOHCI_DBCH_FULL;
1509 fwdma_sync_multiseg(dbch->am, kick->idx, dbch->pdb_tr->idx,
1512 if (dbch->xferq.flag & FWXFERQ_RUNNING)
1513 OWRITE(sc, OHCI_DMACTL(dbch->off), OHCI_CNTL_DMA_WAKE);
1517 OREAD(sc, OHCI_DMACTL(dbch->off)));
1518 OWRITE(sc, OHCI_DMACMD(dbch->off),
1519 dbch->top->bus_addr | fsegment);
1520 OWRITE(sc, OHCI_DMACTL(dbch->off), OHCI_CNTL_DMA_RUN);
1521 dbch->xferq.flag |= FWXFERQ_RUNNING;
1524 dbch->top = db_tr;
1532 struct fwohci_dbch *dbch = &sc->atrq;
1534 mutex_enter(&dbch->xferq.q_mtx);
1535 fwohci_start(sc, dbch);
1536 mutex_exit(&dbch->xferq.q_mtx);
1544 struct fwohci_dbch *dbch = &sc->atrs;
1546 mutex_enter(&dbch->xferq.q_mtx);
1547 fwohci_start(sc, dbch);
1548 mutex_exit(&dbch->xferq.q_mtx);
1553 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1563 if (dbch->off != OHCI_ATQOFF &&
1564 dbch->off != OHCI_ATSOFF)
1567 if (dbch->off == OHCI_ATQOFF)
1572 mutex_enter(&dbch->xferq.q_mtx);
1573 tr = dbch->bottom;
1574 while (dbch->xferq.queued > 0) {
1575 fwdma_sync_multiseg(dbch->am, tr->idx, tr->idx,
1593 OWRITE(sc, OHCI_DMACTLCLR(dbch->off),
1598 OWRITE(sc, OHCI_DMACTLCLR(dbch->off),
1642 dbch->xferq.queued--;
1643 dbch->bottom = STAILQ_NEXT(tr, link);
1647 mutex_exit(&dbch->xferq.q_mtx);
1670 mutex_enter(&dbch->xferq.q_mtx);
1678 if (dbch->bottom == dbch->top) {
1680 if (firewire_debug && dbch->xferq.queued > 0)
1684 tr = dbch->bottom;
1687 if (dbch->xferq.queued > 0 || packets > 0)
1688 fwdma_sync_multiseg(dbch->am, tr->idx, tr->idx,
1690 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1692 dbch->flags &= ~FWOHCI_DBCH_FULL;
1693 fwohci_start(sc, dbch);
1695 mutex_exit(&dbch->xferq.q_mtx);
1699 fwohci_db_free(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1703 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1706 for (last = db_tr = STAILQ_FIRST(&dbch->db_trq); db_tr != last;
1709 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1715 dbch->ndb = 0;
1716 db_tr = STAILQ_FIRST(&dbch->db_trq);
1717 fwdma_free_multiseg(dbch->am);
1719 STAILQ_INIT(&dbch->db_trq);
1720 dbch->flags &= ~FWOHCI_DBCH_INIT;
1721 seldestroy(&dbch->xferq.rsel);
1725 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1730 const int db_tr_sz = sizeof(struct fwohcidb_tr) * dbch->ndb;
1732 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1737 STAILQ_INIT(&dbch->db_trq);
1745 dbch->am = fwdma_malloc_multiseg(fc, DB_SIZE(dbch), DB_SIZE(dbch),
1747 dbch->ndb, BUS_DMA_WAITOK);
1749 dbch->ndb, BUS_DMA_WAITOK |
1750 ((dbch->off == OHCI_ARQOFF || dbch->off == OHCI_ARSOFF) ?
1753 if (dbch->am == NULL) {
1759 for (idb = 0; idb < dbch->ndb; idb++) {
1762 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1763 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1766 if (bus_dmamap_create(fc->dmat, dbch->xferq.psize,
1767 dbch->ndesc > 3 ? dbch->ndesc - 2 : 1, MAX_REQCOUNT, 0,
1770 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1771 fwohci_db_free(sc, dbch);
1774 if (dbch->off == OHCI_ARQOFF ||
1775 dbch->off == OHCI_ARSOFF) {
1777 &db_tr->dma_map, dbch
1782 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1783 fwohci_db_free(sc, dbch);
1787 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1788 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1790 &dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket];
1792 if (idb % dbch->xferq.bnpacket == 0)
1794 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1800 STAILQ_FOREACH(tmpq, &dbch->db_trq, link)
1802 lastq->link.stqe_next = STAILQ_FIRST(&dbch->db_trq);
1804 dbch->xferq.queued = 0;
1805 dbch->pdb_tr = NULL;
1806 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1807 dbch->bottom = dbch->top;
1808 dbch->flags = FWOHCI_DBCH_INIT;
1809 selinit(&dbch->xferq.rsel);
1813 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1820 if (!(dbch->xferq.flag & FWXFERQ_EXTBUF)) {
1824 z = dbch->ndesc;
1826 if (dbch->off == sc->it[dmach].off)
1832 if (dbch->xferq.flag & FWXFERQ_RUNNING)
1834 dbch->xferq.flag |= FWXFERQ_RUNNING;
1835 for (i = 0, dbch->bottom = dbch->top; i < dbch->ndb - 1; i++)
1836 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1837 db_tr = dbch->top;
1838 for (idb = 0; idb < dbch->ndb; idb++) {
1839 fwohci_add_tx_buf(dbch, db_tr, idb);
1847 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1848 if (((idb + 1) % dbch->xferq.bnpacket) == 0) {
1859 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1864 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1870 z = dbch->ndesc;
1871 if (dbch->xferq.flag & FWXFERQ_STREAM) {
1872 if (dbch->xferq.flag & FWXFERQ_RUNNING)
1875 if (dbch->xferq.flag & FWXFERQ_RUNNING) {
1879 dbch->xferq.flag |= FWXFERQ_RUNNING;
1880 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1881 for (i = 0, dbch->bottom = dbch->top; i < dbch->ndb - 1; i++)
1882 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1883 db_tr = dbch->top;
1886 for (idb = 0; idb < dbch->ndb; idb++) {
1887 if (dbch->off == OHCI_ARQOFF ||
1888 dbch->off == OHCI_ARSOFF)
1891 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1898 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1899 if (((idb + 1) % dbch->xferq.bnpacket) == 0) {
1907 FWOHCI_DMA_CLEAR(dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend,
1909 dbch->buf_offset = 0;
1911 fwdma_sync_multiseg_all(dbch->am,
1913 if (!(dbch->xferq.flag & FWXFERQ_STREAM)) {
1914 OWRITE(sc, OHCI_DMACMD(dbch->off), dbch->top->bus_addr | z);
1915 OWRITE(sc, OHCI_DMACTL(dbch->off), OHCI_CNTL_DMA_RUN);
2076 struct fwohci_dbch *dbch = &sc->ir[i];
2078 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
2304 struct fwohci_dbch *dbch;
2308 dbch = &sc->atrq;
2310 dbch = &sc->atrs;
2312 dbch = &sc->arrq;
2314 dbch = &sc->arrs;
2316 dbch = &sc->it[ch - ITX_CH];
2318 dbch = &sc->ir[ch - IRX_CH];
2319 cntl = stat = OREAD(sc, dbch->off);
2320 cmd = OREAD(sc, dbch->off + 0xc);
2321 match = OREAD(sc, dbch->off + 0x10);
2349 struct fwohci_dbch *dbch;
2360 dbch = &sc->atrq;
2362 dbch = &sc->atrs;
2364 dbch = &sc->arrq;
2366 dbch = &sc->arrs;
2368 dbch = &sc->it[ch - ITX_CH];
2370 dbch = &sc->ir[ch - IRX_CH];
2371 cmd = OREAD(sc, dbch->off + 0xc);
2373 if (dbch->ndb == 0) {
2377 pp = dbch->top;
2381 for (idb = 0; idb < dbch->ndb; idb++) {
2390 for (jdb = 0; jdb < dbch->ndesc; jdb++)
2414 print_db(pp, prev, ch, dbch->ndesc);
2417 dbch->ndesc);
2420 print_db(np, next, ch, dbch->ndesc);
2505 struct fwohci_dbch *dbch;
2514 dbch = &sc->it[dmach];
2522 for (idb = 0; idb < dbch->xferq.bnpacket; idb++) {
2542 db[0].db.desc.depend = db[dbch->ndesc - 1].db.desc.depend =
2543 STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2545 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2546 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2553 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2555 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2568 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2575 it = &dbch->xferq;
2600 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2609 rq = &dbch->xferq;
2610 if (rq->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2700 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch,
2718 if (r > dbch->xferq.psize) {
2728 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch,
2732 struct fwohcidb_tr *bdb_tr = dbch->bottom;
2735 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2737 fwdma_sync_multiseg(dbch->am, bdb_tr->idx, bdb_tr->idx,
2739 FWOHCI_DMA_SET(bdb_tr->db[0].db.desc.depend, dbch->ndesc);
2741 fwdma_sync_multiseg(dbch->am, bdb_tr->idx, db_tr->idx,
2743 dbch->bottom = db_tr;
2746 OWRITE(sc, OHCI_DMACTL(dbch->off), OHCI_CNTL_DMA_WAKE);
2750 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
2761 const int psize = dbch->xferq.psize;
2764 if (dbch->off != OHCI_ARQOFF &&
2765 dbch->off != OHCI_ARSOFF)
2769 mutex_enter(&dbch->xferq.q_mtx);
2770 db_tr = dbch->top;
2772 fwdma_sync_multiseg(dbch->am, db_tr->idx, db_tr->idx,
2778 if (dbch->off == OHCI_ARQOFF)
2786 if (dbch->pdb_tr == NULL) {
2787 len -= dbch->buf_offset;
2788 ld += dbch->buf_offset;
2789 m = dbch->buf_offset;
2796 if (dbch->pdb_tr != NULL) {
2801 if (dbch->buf_offset < 0) {
2805 rlen -= dbch->buf_offset;
2806 buf = (char *)dbch->pdb_tr->buf +
2831 buf = (char *)dbch->pdb_tr->buf +
2832 dbch->buf_offset;
2833 rlen = psize - dbch->buf_offset;
2836 rlen, dbch->buf_offset);
2850 dbch->pdb_tr = db_tr;
2851 dbch->buf_offset -= psize;
2864 plen = fwohci_get_plen(sc, dbch, fp) - offset;
2878 dbch->pdb_tr = db_tr;
2943 len, OREAD(sc, OHCI_DMACTL(dbch->off)),
2950 if (dbch->pdb_tr != NULL) {
2951 if (dbch->buf_offset < 0)
2953 dbch->pdb_tr->dma_map,
2954 psize + dbch->buf_offset,
2955 0 - dbch->buf_offset,
2959 dbch->pdb_tr->dma_map,
2960 dbch->buf_offset,
2961 psize - dbch->buf_offset,
2963 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 1);
2964 dbch->pdb_tr = NULL;
2966 dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
2975 dbch->buf_offset = psize - resCount;
2981 if (dbch->pdb_tr == NULL) {
2982 fwohci_arcv_free_buf(sc, dbch, db_tr, 1);
2983 dbch->buf_offset = 0;
2985 if (dbch->pdb_tr != db_tr)
2988 dbch->top = STAILQ_NEXT(db_tr, link);
2990 db_tr = dbch->top;
2991 fwdma_sync_multiseg(dbch->am, db_tr->idx, db_tr->idx,
3002 fwdma_sync_multiseg(dbch->am, db_tr->idx, db_tr->idx,
3004 mutex_exit(&dbch->xferq.q_mtx);
3009 OREAD(sc, OHCI_DMACTL(dbch->off)));
3010 if (dbch->pdb_tr != NULL) {
3011 if (dbch->buf_offset < 0)
3012 bus_dmamap_sync(sc->fc.dmat, dbch->pdb_tr->dma_map,
3013 psize + dbch->buf_offset, 0 - dbch->buf_offset,
3016 bus_dmamap_sync(sc->fc.dmat, dbch->pdb_tr->dma_map,
3017 dbch->buf_offset, psize - dbch->buf_offset,
3019 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr, 1);
3020 dbch->pdb_tr = NULL;
3026 fwohci_arcv_free_buf(sc, dbch, db_tr, 0);
3032 dbch->top = db_tr;
3033 dbch
3034 OWRITE(sc, OHCI_DMACTL(dbch->off), OHCI_CNTL_DMA_WAKE);
3035 fwdma_sync_multiseg(dbch->am, db_tr->idx, db_tr->idx,
3039 mutex_exit(&dbch->xferq.q_mtx);
Indexes created Wed Oct 01 19:09:53 GMT 2025