Lines Matching refs:fwohcireg_t
97 typedef uint32_t fwohcireg_t;
193 fwohcireg_t cntl;
210 fwohcireg_t cntl_clr;
211 fwohcireg_t dummy0;
212 fwohcireg_t cmd;
213 fwohcireg_t match;
214 fwohcireg_t dummy1;
215 fwohcireg_t dummy2;
216 fwohcireg_t dummy3;
220 fwohcireg_t cntl;
221 fwohcireg_t cntl_clr;
222 fwohcireg_t dummy0;
223 fwohcireg_t cmd;
227 fwohcireg_t ver; /* Version No. 0x0 */
228 fwohcireg_t guid; /* GUID_ROM No. 0x4 */
229 fwohcireg_t retry; /* AT retries 0x8 */
231 fwohcireg_t csr_data; /* CSR data 0xc */
232 fwohcireg_t csr_cmp; /* CSR compare 0x10 */
233 fwohcireg_t csr_cntl; /* CSR compare 0x14 */
234 fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */
235 fwohcireg_t bus_id; /* BUS_ID 0x1c */
236 fwohcireg_t bus_opt; /* BUS option 0x20 */
239 fwohcireg_t guid_hi; /* GUID hi 0x24 */
240 fwohcireg_t guid_lo; /* GUID lo 0x28 */
241 fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */
242 fwohcireg_t config_rom; /* config ROM map 0x34 */
243 fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */
244 fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */
245 fwohcireg_t vendor; /* vendor ID 0x40 */
246 fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */
247 fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */
248 fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */
257 fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */
258 fwohcireg_t dummy3[1]; /* dummy 0x60 */
259 fwohcireg_t sid_buf; /* self id buffer 0x64 */
260 fwohcireg_t sid_cnt; /* self id count 0x68 */
261 fwohcireg_t dummy4[1]; /* dummy 0x6c */
262 fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */
263 fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */
264 fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */
265 fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */
270 fwohcireg_t int_stat; /* 0x80 */
271 fwohcireg_t int_clear; /* 0x84 */
272 fwohcireg_t int_mask; /* 0x88 */
273 fwohcireg_t int_mask_clear; /* 0x8c */
274 fwohcireg_t it_int_stat; /* 0x90 */
275 fwohcireg_t it_int_clear; /* 0x94 */
276 fwohcireg_t it_int_mask; /* 0x98 */
277 fwohcireg_t it_mask_clear; /* 0x9c */
278 fwohcireg_t ir_int_stat; /* 0xa0 */
279 fwohcireg_t ir_int_clear; /* 0xa4 */
280 fwohcireg_t ir_int_mask; /* 0xa8 */
281 fwohcireg_t ir_mask_clear; /* 0xac */
282 fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */
283 fwohcireg_t fairness; /* fairness control 0xdc */
284 fwohcireg_t link_cntl; /* Chip control 0xe0*/
285 fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/
287 fwohcireg_t node; /* Node ID 0xe8 */
293 fwohcireg_t phy_access; /* PHY cntl 0xec */
302 fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */
303 fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */
304 fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */
305 fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */
306 fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */
307 fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */
308 fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */
309 fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */
310 fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */
311 fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */
313 fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */
315 fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */
Indexes created Wed Oct 22 00:09:40 GMT 2025