Lines Matching refs:gt
1 /* $NetBSD: gt.c,v 1.30 2021/08/07 16:19:13 thorpej Exp $ */
41 * gt.c -- GT system controller driver
45 __KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.30 2021/08/07 16:19:13 thorpej Exp $");
244 gt_attach_common(struct gt_softc *gt)
251 gt_write(gt, GTPCI_CA(0), PCI_ID_REG);
252 gt->sc_model = PCI_PRODUCT(gt_read(gt, GTPCI_CD(0)));
253 gt_write(gt, GTPCI_CA(0), PCI_CLASS_REG);
254 gt->sc_rev = PCI_REVISION(gt_read(gt, GTPCI_CD(0)));
257 switch (gt->sc_model) {
259 aprint_normal(": GT-6426x%c Discovery\n",
260 (gt->sc_rev == MARVELL_DISCOVERY_REVA) ? 'A' : 'B');
279 cpumode = gt_read(gt, GT_CPU_Mode);
280 aprint_normal_dev(gt->sc_dev,
293 cpumstr = gt_read(gt, GT_CPU_Master_Ctl);
302 gt_read(gt, GT_WDOG_Config), gt_read(gt, GT_WDOG_Value));
305 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS0_Low_Decode), gt->sc_model);
306 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS0_High_Decode), gt->sc_model);
307 aprint_normal_dev(gt->sc_dev, " scs[0]=%#10x-%#10x\n",
310 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS1_Low_Decode), gt->sc_model);
311 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS1_High_Decode), gt->sc_model);
312 aprint_normal_dev(gt->sc_dev, " scs[1]=%#10x-%#10x\n",
315 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS2_Low_Decode), gt->sc_model);
316 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS2_High_Decode), gt->sc_model);
317 aprint_normal_dev(gt->sc_dev, " scs[2]=%#10x-%#10x\n",
320 loaddr = GT_LADDR_GET(gt_read(gt, GT_SCS3_Low_Decode), gt->sc_model);
321 hiaddr = GT_HADDR_GET(gt_read(gt, GT_SCS3_High_Decode), gt->sc_model);
322 aprint_normal_dev(gt->sc_dev, " scs[3]=%#10x-%#10x\n",
325 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS0_Low_Decode), gt->sc_model);
326 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS0_High_Decode), gt->sc_model);
327 aprint_normal_dev(gt->sc_dev, " cs[0]=%#10x-%#10x\n",
330 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS1_Low_Decode), gt->sc_model);
331 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS1_High_Decode), gt->sc_model);
332 aprint_normal_dev(gt->sc_dev, " cs[1]=%#10x-%#10x\n",
335 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS2_Low_Decode), gt->sc_model);
336 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS2_High_Decode), gt->sc_model);
337 aprint_normal_dev(gt->sc_dev, " cs[2]=%#10x-%#10x\n",
340 loaddr = GT_LADDR_GET(gt_read(gt, GT_CS3_Low_Decode), gt->sc_model);
341 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CS3_High_Decode), gt->sc_model);
342 aprint_normal_dev(gt->sc_dev, " cs[3]=%#10x-%#10x\n",
345 loaddr = GT_LADDR_GET(gt_read(gt, GT_BootCS_Low_Decode), gt->sc_model);
346 hiaddr = GT_HADDR_GET(gt_read(gt, GT_BootCS_High_Decode), gt->sc_model);
347 aprint_normal_dev(gt->sc_dev, " bootcs=%#10x-%#10x\n",
350 loaddr = GT_LADDR_GET(gt_read(gt, GT_PCI0_IO_Low_Decode), gt->sc_model);
352 GT_HADDR_GET(gt_read(gt, GT_PCI0_IO_High_Decode), gt->sc_model);
353 aprint_normal_dev(gt->sc_dev, " pci0io=%#10x-%#10x ",
356 loaddr = gt_read(gt, GT_PCI0_IO_Remap);
360 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem0_Low_Decode), gt->sc_model);
362 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem0_High_Decode), gt->sc_model);
363 aprint_normal_dev(gt->sc_dev, " pci0mem[0]=%#10x-%#10x ",
366 loaddr = gt_read(gt, GT_PCI0_Mem0_Remap_Low);
367 hiaddr = gt_read(gt, GT_PCI0_Mem0_Remap_High);
371 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem1_Low_Decode), gt->sc_model);
373 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem1_High_Decode), gt->sc_model);
374 aprint_normal_dev(gt->sc_dev, " pci0mem[1]=%#10x-%#10x ",
377 loaddr = gt_read(gt, GT_PCI0_Mem1_Remap_Low);
378 hiaddr = gt_read(gt, GT_PCI0_Mem1_Remap_High);
382 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem2_Low_Decode), gt->sc_model);
384 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem2_High_Decode), gt->sc_model);
385 aprint_normal_dev(gt->sc_dev, " pci0mem[2]=%#10x-%#10x ",
388 loaddr = gt_read(gt, GT_PCI0_Mem2_Remap_Low);
389 hiaddr = gt_read(gt, GT_PCI0_Mem2_Remap_High);
393 GT_LADDR_GET(gt_read(gt, GT_PCI0_Mem3_Low_Decode), gt->sc_model);
395 GT_HADDR_GET(gt_read(gt, GT_PCI0_Mem3_High_Decode), gt->sc_model);
396 aprint_normal_dev(gt->sc_dev, " pci0mem[3]=%#10x-%#10x ",
399 loaddr = gt_read(gt, GT_PCI0_Mem3_Remap_Low);
400 hiaddr = gt_read(gt, GT_PCI0_Mem3_Remap_High);
403 loaddr = GT_LADDR_GET(gt_read(gt, GT_PCI1_IO_Low_Decode), gt->sc_model);
405 GT_HADDR_GET(gt_read(gt, GT_PCI1_IO_High_Decode), gt->sc_model);
406 aprint_normal_dev(gt->sc_dev, " pci1io=%#10x-%#10x ",
409 loaddr = gt_read(gt, GT_PCI1_IO_Remap);
413 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem0_Low_Decode), gt->sc_model);
415 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem0_High_Decode), gt->sc_model);
416 aprint_normal_dev(gt->sc_dev, " pci1mem[0]=%#10x-%#10x ",
419 loaddr = gt_read(gt, GT_PCI1_Mem0_Remap_Low);
420 hiaddr = gt_read(gt, GT_PCI1_Mem0_Remap_High);
424 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem1_Low_Decode), gt->sc_model);
426 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem1_High_Decode), gt->sc_model);
427 aprint_normal_dev(gt->sc_dev, " pci1mem[1]=%#10x-%#10x ",
430 loaddr = gt_read(gt, GT_PCI1_Mem1_Remap_Low);
431 hiaddr = gt_read(gt, GT_PCI1_Mem1_Remap_High);
435 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem2_Low_Decode), gt->sc_model);
437 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem2_High_Decode), gt->sc_model);
438 aprint_normal_dev(gt->sc_dev, " pci1mem[2]=%#10x-%#10x ",
441 loaddr = gt_read(gt, GT_PCI1_Mem2_Remap_Low);
442 hiaddr = gt_read(gt, GT_PCI1_Mem2_Remap_High);
446 GT_LADDR_GET(gt_read(gt, GT_PCI1_Mem3_Low_Decode), gt->sc_model);
448 GT_HADDR_GET(gt_read(gt, GT_PCI1_Mem3_High_Decode), gt->sc_model);
449 aprint_normal_dev(gt->sc_dev, " pci1mem[3]=%#10x-%#10x ",
452 loaddr = gt_read(gt, GT_PCI1_Mem3_Remap_Low);
453 hiaddr = gt_read(gt, GT_PCI1_Mem3_Remap_High);
456 loaddr = GT_LADDR_GET(gt_read(gt, GT_Internal_Decode), gt->sc_model);
457 aprint_normal_dev(gt->sc_dev, " internal=%#10x-%#10x\n",
460 loaddr = GT_LADDR_GET(gt_read(gt, GT_CPU0_Low_Decode), gt->sc_model);
461 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CPU0_High_Decode), gt->sc_model);
462 aprint_normal_dev(gt->sc_dev, " cpu0=%#10x-%#10x\n",
466 loaddr = GT_LADDR_GET(gt_read(gt, GT_CPU1_Low_Decode), gt->sc_model);
467 hiaddr = GT_HADDR_GET(gt_read(gt, GT_CPU1_High_Decode), gt->sc_model);
468 aprint_normal_dev(gt->sc_dev, " cpu1=%#10x-%#10x",
473 aprint_normal("%s:", device_xname(gt->sc_dev));
475 cpucfg = gt_read(gt, GT_CPU_Cfg);
478 gt_write(gt, GT_CPU_Cfg, cpucfg);
494 gt_watchdog_init(gt);
498 gt_devbus_intr_enb(gt);
501 gt_ecc_intr_enb(gt);
504 gt_sdma_intr_enb(gt);
507 gt_comm_intr_enb(gt);
510 gt_attach_peripherals(gt);
514 gt_watchdog_enable(gt);
523 struct gt_softc *gt = (struct gt_softc *)arg;
527 cause = gt_read(gt, GT_DEVBUS_ICAUSE);
528 addr = gt_read(gt, GT_DEVBUS_ERR_ADDR);
529 gt_write(gt, GT_DEVBUS_ICAUSE, 0); /* clear intr */
532 aprint_error_dev(gt->sc_dev,
539 aprint_error_dev(gt->sc_dev,
550 * gt_devbus_intr_enb - enable GT-64260 Device Bus interrupts
553 gt_devbus_intr_enb(struct gt_softc *gt)
555 gt_write(gt, GT_DEVBUS_IMASK,
557 (void)gt_read(gt, GT_DEVBUS_ERR_ADDR); /* clear addr */
558 gt_write(gt, GT_DEVBUS_ICAUSE, 0); /* clear intr */
560 (void)marvell_intr_establish(IRQ_DEV, IPL_VM, gt_devbus_intr, gt);
575 struct gt_softc *gt = (struct gt_softc *)arg;
579 count = gt_read(gt, GT_ECC_Count);
580 dlo = gt_read(gt, GT_ECC_Data_Lo);
581 dhi = gt_read(gt, GT_ECC_Data_Hi);
582 rec = gt_read(gt, GT_ECC_Rec);
583 calc = gt_read(gt, GT_ECC_Calc);
584 addr = gt_read(gt, GT_ECC_Addr); /* read last! */
585 gt_write(gt, GT_ECC_Addr, 0); /* clear intr */
589 aprint_error_dev(gt->sc_dev,
600 * gt_ecc_intr_enb - enable GT-64260 ECC interrupts
603 gt_ecc_intr_enb(struct gt_softc *gt)
607 ctl = gt_read(gt, GT_ECC_Ctl);
609 gt_write(gt, GT_ECC_Ctl, ctl);
610 (void)gt_read(gt, GT_ECC_Data_Lo);
611 (void)gt_read(gt, GT_ECC_Data_Hi);
612 (void)gt_read(gt, GT_ECC_Rec);
613 (void)gt_read(gt, GT_ECC_Calc);
614 (void)gt_read(gt, GT_ECC_Addr); /* read last! */
615 gt_write(gt, GT_ECC_Addr, 0); /* clear intr */
617 (void)marvell_intr_establish(IRQ_ECC, IPL_VM, gt_ecc_intr, gt);
623 * gt_sdma_intr_enb - enable GT-64260 SDMA interrupts
626 gt_sdma_intr_enb(struct gt_softc *gt)
629 (void)marvell_intr_establish(IRQ_SDMA, IPL_SERIAL, gtmpsc_intr, gt);
658 struct gt_softc *gt = (struct gt_softc *)arg;
663 cause = gt_read(gt, GT_CommUnitIntr_Cause);
664 gt_write(gt, GT_CommUnitIntr_Cause, ~cause);
665 addr = gt_read(gt, GT_CommUnitIntr_ErrAddr);
667 aprint_error_dev(gt->sc_dev,
678 printf("%s: Comm Unit %s:", device_xname(gt->sc_dev),
694 * gt_comm_intr_init - enable GT-64260 Comm Unit interrupts
697 gt_comm_intr_enb(struct gt_softc *gt)
701 cause = gt_read(gt, GT_CommUnitIntr_Cause);
703 gt_write(gt, GT_CommUnitIntr_Cause, ~cause);
704 gt_write(gt, GT_CommUnitIntr_Mask, GT_CommUnitIntr_DFLT);
705 (void)gt_read(gt, GT_CommUnitIntr_ErrAddr);
707 (void)marvell_intr_establish(IRQ_COMM, IPL_VM, gt_comm_intr, gt);
715 gt_watchdog_init(struct gt_softc *gt)
719 aprint_normal_dev(gt->sc_dev, "watchdog");
724 r = gt_read(gt, GT_WDOG_Config);
725 aprint_normal(" status %#x,%#x:", r, gt_read(gt, GT_WDOG_Value));
727 gt_watchdog_sc = gt; /* enabled */
730 gt_watchdog_disable(gt);
738 gt_watchdog_init(struct gt_softc *gt)
741 aprint_normal_dev(gt->sc_dev, "watchdog not configured\n");
748 gt_watchdog_init(struct gt_softc *gt)
755 aprint_normal_dev(gt->sc_dev, "watchdog");
761 * on GT-64260A we always see 0xffffffff
764 r = gt_read(gt, GT_WDOG_Config);
767 gt_write(gt, GT_WDOG_Config,
769 gt_write(gt, GT_WDOG_Config,
799 r = gt_read(gt, regoff);
802 gt_write(gt, regoff, r);
805 gt_write(gt, GT_WDOG_Value, GT_WDOG_NMI_DFLT);
807 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1a|GT_WDOG_Preset_DFLT);
808 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1b|GT_WDOG_Preset_DFLT);
810 r = gt_read(gt, GT_WDOG_Config);
812 r, gt_read(gt, GT_WDOG_Value),
818 gt_watchdog_enable(struct gt_softc *gt)
824 gt_write(gt, GT_WDOG_Config,
826 gt_write(gt, GT_WDOG_Config,
833 gt_watchdog_disable(struct gt_softc *gt)
839 gt_write(gt, GT_WDOG_Config,
841 gt_write(gt, GT_WDOG_Config,
857 struct gt_softc *gt = gt_watchdog_sc;
859 if ((gt == NULL) || (gt_watchdog_state == 0))
866 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl2a|GT_WDOG_Preset_DFLT);
867 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl2b|GT_WDOG_Preset_DFLT);
876 struct gt_softc *gt = gt_watchdog_sc;
879 r = gt_read(gt, GT_WDOG_Config);
880 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1a);
881 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1b);
886 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1a);
887 gt_write(gt, GT_WDOG_Config, GT_WDOG_Config_Ctl1b);
Indexes created Thu Oct 30 03:10:01 GMT 2025