Cross Reference: /src/sys/dev/marvell/if

Lines Matching defs:rxq
127 #define GE_RXDSYNC(sc, rxq, n, ops) \
128 	bus_dmamap_sync((sc)->sc_dmat, (rxq)->rxq_desc_mem.gdm_map, \
129 	    (n) * sizeof((rxq)->rxq_descs[0]), sizeof((rxq)->rxq_descs[0]), \
131 #define	GE_RXDPRESYNC(sc, rxq, n) \
132 	GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE)
133 #define	GE_RXDPOSTSYNC(sc, rxq, n) \
134 	GE_RXDSYNC(sc, rxq, n, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)
758 	struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio];
764 	error = gfe_dmamem_alloc(sc, &rxq->rxq_desc_mem, 1,
771 	error = gfe_dmamem_alloc(sc, &rxq->rxq_buf_mem, GE_RXBUF_NSEGS,
784 	struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio];
801 		KASSERT(rxq->rxq_desc_mem.gdm_kva != NULL);
802 		KASSERT(rxq->rxq_buf_mem.gdm_kva != NULL);
805 	memset(rxq->rxq_desc_mem.gdm_kva, 0, GE_RXDESC_MEMSIZE);
807 	rxq->rxq_descs =
808 	    (volatile struct gt_eth_desc *) rxq->rxq_desc_mem.gdm_kva;
809 	rxq->rxq_desc_busaddr = rxq->rxq_desc_mem.gdm_map->dm_segs[0].ds_addr;
810 	rxq->rxq_bufs = (struct gfe_rxbuf *) rxq->rxq_buf_mem.gdm_kva;
811 	rxq->rxq_fi = 0;
812 	rxq->rxq_active = GE_RXDESC_MAX;
814 	ds = rxq->rxq_buf_mem.gdm_map->dm_segs;
815 	nxtaddr = rxq->rxq_desc_busaddr + sizeof(*rxd);
816 	for (idx = 0, rxd = rxq->rxq_descs; idx < GE_RXDESC_MAX;
825 			nxtaddr = rxq->rxq_desc_busaddr;
833 	bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map, 0,
834 			rxq->rxq_desc_mem.gdm_map->dm_mapsize,
836 	bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map, 0,
837 			rxq->rxq_buf_mem.gdm_map->dm_mapsize,
840 	rxq->rxq_intrbits = ETH_IR_RxBuffer | ETH_IR_RxError;
843 		rxq->rxq_intrbits |= ETH_IR_RxBuffer_3 | ETH_IR_RxError_3;
844 		rxq->rxq_efrdp = ETH_EFRDP3;
845 		rxq->rxq_ecrdp = ETH_ECRDP3;
848 		rxq->rxq_intrbits |= ETH_IR_RxBuffer_2 | ETH_IR_RxError_2;
849 		rxq->rxq_efrdp = ETH_EFRDP2;
850 		rxq->rxq_ecrdp = ETH_ECRDP2;
853 		rxq->rxq_intrbits |= ETH_IR_RxBuffer_1 | ETH_IR_RxError_1;
854 		rxq->rxq_efrdp = ETH_EFRDP1;
855 		rxq->rxq_ecrdp = ETH_ECRDP1;
858 		rxq->rxq_intrbits |= ETH_IR_RxBuffer_0 | ETH_IR_RxError_0;
859 		rxq->rxq_efrdp = ETH_EFRDP0;
860 		rxq->rxq_ecrdp = ETH_ECRDP0;
871 	struct gfe_rxqueue * const rxq = &sc->sc_rxq[rxprio];
872 	struct mbuf *m = rxq->rxq_curpkt;
877 	while (rxq->rxq_active > 0) {
878 		volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[rxq->rxq_fi];
879 		struct gfe_rxbuf *rxb = &rxq->rxq_bufs[rxq->rxq_fi];
884 		GE_RXDPOSTSYNC(sc, rxq, rxq->rxq_fi);
886 		GE_DPRINTF(sc, (":%d=%#x", rxq->rxq_fi, cmdsts));
887 		rxq->rxq_cmdsts = cmdsts;
895 			GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi);
908 			--rxq->rxq_active;
935 		rxq->rxq_cmdsts = cmdsts;
936 		--rxq->rxq_active;
938 		bus_dmamap_sync(sc->sc_dmat, rxq->rxq_buf_mem.gdm_map,
939 		    rxq->rxq_fi * sizeof(*rxb), buflen, BUS_DMASYNC_POSTREAD);
948 		    (rxq->rxq_cmdsts & RX_STS_M) == 0 ||
949 		    (rxq->rxq_cmdsts & RX_STS_HE) ||
961 		rxq->rxq_cmdsts = 0;
968 		    rxq->rxq_fi,
972 		GE_RXDPRESYNC(sc, rxq, rxq->rxq_fi);
973 		if (++rxq->rxq_fi == GE_RXDESC_MAX)
974 			rxq->rxq_fi = 0;
975 		rxq->rxq_active++;
977 	rxq->rxq_curpkt = m;
985 	struct gfe_rxqueue *rxq;
1004 		rxq = &sc->sc_rxq[rxprio];
1005 		sc->sc_idlemask |= (rxq->rxq_intrbits & ETH_IR_RxBits);
1006 		intrmask &= ~(rxq->rxq_intrbits & ETH_IR_RxBits);
1013 		    device_xname(sc->sc_dev), rxprio, rxq->rxq_fi));
1015 		bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map,
1016 		    0, rxq->rxq_desc_mem.gdm_size,
1019 			volatile struct gt_eth_desc *rxd = &rxq->rxq_descs[idx];
1024 		bus_dmamap_sync(sc->sc_dmat, rxq->rxq_desc_mem.gdm_map,
1025 		    0, rxq->rxq_desc_mem.gdm_size,
1029 		    device_xname(sc->sc_dev), rxprio, rxq->rxq_fi,
1030 		    rxq->rxq_cmdsts, masks[0], masks[1]);
1043 	struct gfe_rxqueue *rxq;
1051 	rxq = &sc->sc_rxq[GE_RXPRIO_HI];
1053 		GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr);
1054 		GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr);
1056 	sc->sc_intrmask |= rxq->rxq_intrbits;
1062 		rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI];
1063 		GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr);
1064 		GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr);
1065 		sc->sc_intrmask |= rxq->rxq_intrbits;
1072 		rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO];
1073 		GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr);
1074 		GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr);
1075 		sc->sc_intrmask |= rxq->rxq_intrbits;
1082 		rxq = &sc->sc_rxq[GE_RXPRIO_LO];
1083 		GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr);
1084 		GE_WRITE(sc, ETH_ECRDP0, rxq->rxq_desc_busaddr);
1085 		sc->sc_intrmask |= rxq->rxq_intrbits;
1096 	struct gfe_rxqueue *rxq = &sc->sc_rxq[rxprio];
1098 	if (rxq == NULL) {
1103 	m_freem(rxq->rxq_curpkt);
1105 		gfe_dmamem_free(sc, &rxq->rxq_desc_mem);
1106 		gfe_dmamem_free(sc, &rxq->rxq_buf_mem);
1150 			struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_HI];
1151 			rxq->rxq_fi = 0;
1152 			GE_WRITE(sc, ETH_EFRDP3, rxq->rxq_desc_busaddr);
1153 			GE_WRITE(sc, ETH_ECRDP3, rxq->rxq_desc_busaddr);
1156 			struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDHI];
1157 			rxq->rxq_fi = 0;
1158 			GE_WRITE(sc, ETH_EFRDP2, rxq->rxq_desc_busaddr);
1159 			GE_WRITE(sc, ETH_ECRDP2, rxq->rxq_desc_busaddr);
1162 			struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_MEDLO];
1163 			rxq->rxq_fi = 0;
1164 			GE_WRITE(sc, ETH_EFRDP1, rxq->rxq_desc_busaddr);
1165 			GE_WRITE(sc, ETH_ECRDP1, rxq->rxq_desc_busaddr);
1168 			struct gfe_rxqueue *rxq = &sc->sc_rxq[GE_RXPRIO_LO];
1169 			rxq->rxq_fi = 0;
1170 			GE_WRITE(sc, ETH_EFRDP0, rxq->rxq_desc_busaddr);
1171 rxq->rxq_desc_busaddr);
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