Cross Reference: /src/sys/dev/mii/ikphyreg.h

Lines Matching defs:GG82563_REG
43 #define GG82563_REG(page, reg)    \
51 #define GG82563_PHY_SPEC_CTRL	GG82563_REG(0, 16) /* PHY Specific Control */
70 #define GG82563_PHY_SPEC_STATUS	GG82563_REG(0, 17) /* PHY Specific Status */
89         GG82563_REG(0, 18) /* Interrupt Enable */
91 #define GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) /* PHY Specific Status 2 */
106 #define GG82563_PHY_RX_ERR_CNTR	GG82563_REG(0, 21) /* Receive Error Counter */
108 #define GG82563_PHY_PAGE_SELECT	GG82563_REG(0, 22) /* Page Select */
110 #define GG82563_PHY_SPEC_CTRL_2	GG82563_REG(0, 26) /* PHY Specific Control 2 */
122 #define GG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) /* Alternate Page Select */
123 #define GG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */
125 #define GG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) /* MAC Specific Control Register */
134 #define GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) /* MAC Specific Control 2 */
136 #define GG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) /* DSP Distance */
144 #define GG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) /* Kumeran Mode Control */
152 #define GG82563_PHY_PORT_RESET	GG82563_REG(193, 17) /* Port Reset */
154 #define GG82563_PHY_REVISION_ID	GG82563_REG(193, 18) /* Revision ID */
156 #define GG82563_PHY_DEVICE_ID	GG82563_REG(193, 19) /* Device ID */
158 #define GG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) /* Power Management Control */
174 #define GG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) /* Rate Adaptation Control */
177 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) /* FIFO's Control/Status */
179 #define GG82563_PHY_KMRN_CTRL	GG82563_REG(194, 17) /* Control */
181 #define GG82563_PHY_INBAND_CTRL	GG82563_REG(194, 18) /* Inband Control */
184 #define GG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) /* Diagnostic */
186 #define GG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) /* Acknowledge Timeouts */
188 #define GG82563_PHY_ADV_ABILITY	GG82563_REG(194, 21) /* Advertised Ability */
190 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY GG82563_REG(194, 23) /* Link Partner Advertised Ability */
192 #define GG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) /* Advertised Next Page */
194 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE GG82563_REG(194, 25) /* Link Partner Advertised Next page */
196 #define GG82563_PHY_KMRN_MISC	GG82563_REG(194, 26) /* Misc. */
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