Lines Matching refs:cpudata
940 struct vmx_cpudata *cpudata = vcpu->cpudata;
943 cpudata->vmcs_refcnt++;
944 if (cpudata->vmcs_refcnt > 1) {
946 KASSERT(vmx_vmptrst() == cpudata->vmcs_pa);
950 vmcs_ci = cpudata->vmcs_ci;
951 cpudata->vmcs_ci = (void *)0x00FFFFFFFFFFFFFF; /* clobber */
957 vmx_vmclear(&cpudata->vmcs_pa);
958 cpudata->vmcs_launched = false;
961 vmx_vmclear_remote(vmcs_ci, cpudata->vmcs_pa);
962 cpudata->vmcs_launched = false;
967 vmx_vmptrld(&cpudata->vmcs_pa);
973 struct vmx_cpudata *cpudata = vcpu->cpudata;
976 KASSERT(vmx_vmptrst() == cpudata->vmcs_pa);
977 KASSERT(cpudata->vmcs_refcnt > 0);
978 cpudata->vmcs_refcnt--;
980 if (cpudata->vmcs_refcnt > 0) {
984 cpudata->vmcs_ci = curcpu();
991 struct vmx_cpudata *cpudata = vcpu->cpudata;
994 KASSERT(vmx_vmptrst() == cpudata->vmcs_pa);
995 KASSERT(cpudata->vmcs_refcnt == 1);
996 cpudata->vmcs_refcnt--;
998 vmx_vmclear(&cpudata->vmcs_pa);
1007 struct vmx_cpudata *cpudata = vcpu->cpudata;
1015 cpudata->nmi_window_exit = true;
1018 cpudata->int_window_exit = true;
1027 struct vmx_cpudata *cpudata = vcpu->cpudata;
1034 cpudata->nmi_window_exit = false;
1037 cpudata->int_window_exit = false;
1079 struct vmx_cpudata *cpudata = vcpu->cpudata;
1125 cpudata->evt_pending = true;
1230 vmx_inkernel_exec_cpuid(struct vmx_cpudata *cpudata, uint64_t eax, uint64_t ecx)
1235 cpudata->gprs[NVMM_X64_GPR_RAX] = descs[0];
1236 cpudata->gprs[NVMM_X64_GPR_RBX] = descs[1];
1237 cpudata->gprs[NVMM_X64_GPR_RCX] = descs[2];
1238 cpudata->gprs[NVMM_X64_GPR_RDX] = descs[3];
1245 struct vmx_cpudata *cpudata = vcpu->cpudata;
1268 vmx_inkernel_exec_cpuid(cpudata, eax, ecx);
1273 vmx_inkernel_exec_cpuid(cpudata, eax, ecx);
1278 vmx_inkernel_exec_cpuid(cpudata, eax, ecx);
1288 cpudata->gprs[NVMM_X64_GPR_RAX] = vmx_cpuid_max_basic;
1291 cpudata->gprs[NVMM_X64_GPR_RAX] &= nvmm_cpuid_00000001.eax;
1293 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~CPUID_LOCAL_APIC_ID;
1294 cpudata->gprs[NVMM_X64_GPR_RBX] |= __SHIFTIN(vcpu->cpuid,
1297 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000001.ecx;
1298 cpudata->gprs[NVMM_X64_GPR_RCX] |= CPUID2_RAZ;
1300 cpudata->gprs[NVMM_X64_GPR_RCX] |= CPUID2_PCID;
1303 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000001.edx;
1308 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~CPUID2_OSXSAVE;
1314 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1315 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1316 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1317 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1323 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1324 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1325 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1326 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1331 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1332 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_00000007.ebx;
1333 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_00000007.ecx;
1334 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_00000007.edx;
1336 cpudata->gprs[NVMM_X64_GPR_RBX] |= CPUID_SEF_INVPCID;
1340 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1341 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1342 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1343 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1349 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1350 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1351 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1352 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1355 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1356 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1357 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1358 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1363 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1364 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1365 cpudata->gprs[NVMM_X64_GPR_RCX] =
1368 cpudata->gprs[NVMM_X64_GPR_RDX] = vcpu->cpuid;
1372 cpudata->gprs[NVMM_X64_GPR_RAX] = ilog2(ncpus);
1373 cpudata->gprs[NVMM_X64_GPR_RBX] = ncpus;
1374 cpudata->gprs[NVMM_X64_GPR_RCX] =
1377 cpudata->gprs[NVMM_X64_GPR_RDX] = vcpu->cpuid;
1380 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1381 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1382 cpudata->gprs[NVMM_X64_GPR_RCX] = 0; /* LVLTYPE_INVAL */
1383 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1388 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1389 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1390 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1391 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1399 cpudata->gprs[NVMM_X64_GPR_RAX] = vmx_xcr0_mask & 0xFFFFFFFF;
1400 if (cpudata->gxcr0 & XCR0_SSE) {
1401 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct fxsave);
1403 cpudata->gprs[NVMM_X64_GPR_RBX] = sizeof(struct save87);
1405 cpudata->gprs[NVMM_X64_GPR_RBX] += 64; /* XSAVE header */
1406 cpudata->gprs[NVMM_X64_GPR_RCX] = sizeof(struct fxsave) + 64;
1407 cpudata->gprs[NVMM_X64_GPR_RDX] = vmx_xcr0_mask >> 32;
1410 cpudata->gprs[NVMM_X64_GPR_RAX] &=
1413 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1414 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1415 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1418 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1419 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1420 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1421 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1428 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1429 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1430 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1431 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1437 cpudata->gprs[NVMM_X64_GPR_RAX] = 0;
1438 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1439 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1440 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1450 cpudata->gprs[NVMM_X64_GPR_RAX] = VMX_CPUID_MAX_HYPERVISOR;
1451 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1452 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1453 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1454 memcpy(&cpudata->gprs[NVMM_X64_GPR_RBX], "___ ", 4);
1455 memcpy(&cpudata->gprs[NVMM_X64_GPR_RCX], "NVMM", 4);
1456 memcpy(&cpudata->gprs[NVMM_X64_GPR_RDX], " ___", 4);
1459 cpudata->gprs[NVMM_X64_GPR_RAX] = curcpu()->ci_data.cpu_cc_freq / 1000;
1461 cpudata->gprs[NVMM_X64_GPR_RBX] = lapic_per_second / 1000;
1463 cpudata->gprs[NVMM_X64_GPR_RBX] = 0;
1464 cpudata->gprs[NVMM_X64_GPR_RCX] = 0;
1465 cpudata->gprs[NVMM_X64_GPR_RDX] = 0;
1472 cpudata->gprs[NVMM_X64_GPR_RAX] = vmx_cpuid_max_extended;
1475 cpudata->gprs[NVMM_X64_GPR_RAX] &= nvmm_cpuid_80000001.eax;
1476 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000001.ebx;
1477 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000001.ecx;
1478 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000001.edx;
1487 cpudata->gprs[NVMM_X64_GPR_RAX] &= nvmm_cpuid_80000007.eax;
1488 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000007.ebx;
1489 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000007.ecx;
1490 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000007.edx;
1493 cpudata->gprs[NVMM_X64_GPR_RAX] &= nvmm_cpuid_80000008.eax;
1494 cpudata->gprs[NVMM_X64_GPR_RBX] &= nvmm_cpuid_80000008.ebx;
1495 cpudata->gprs[NVMM_X64_GPR_RCX] &= nvmm_cpuid_80000008.ecx;
1496 cpudata->gprs[NVMM_X64_GPR_RDX] &= nvmm_cpuid_80000008.edx;
1519 struct vmx_cpudata *cpudata = vcpu->cpudata;
1524 eax = cpudata->gprs[NVMM_X64_GPR_RAX];
1525 ecx = cpudata->gprs[NVMM_X64_GPR_RCX];
1526 vmx_inkernel_exec_cpuid(cpudata, eax, ecx);
1530 if (!cpudata->cpuidpresent[i]) {
1533 cpuid = &cpudata->cpuid[i];
1545 cpudata->gprs[NVMM_X64_GPR_RAX] &= ~cpuid->u.mask.del.eax;
1546 cpudata->gprs[NVMM_X64_GPR_RBX] &= ~cpuid->u.mask.del.ebx;
1547 cpudata->gprs[NVMM_X64_GPR_RCX] &= ~cpuid->u.mask.del.ecx;
1548 cpudata->gprs[NVMM_X64_GPR_RDX] &= ~cpuid->u.mask.del.edx;
1551 cpudata->gprs[NVMM_X64_GPR_RAX] |= cpuid->u.mask.set.eax;
1552 cpudata->gprs[NVMM_X64_GPR_RBX] |= cpuid->u.mask.set.ebx;
1553 cpudata->gprs[NVMM_X64_GPR_RCX] |= cpuid->u.mask.set.ecx;
1554 cpudata->gprs[NVMM_X64_GPR_RDX] |= cpuid->u.mask.set.edx;
1567 struct vmx_cpudata *cpudata = vcpu->cpudata;
1570 if (cpudata->int_window_exit) {
1609 struct vmx_cpudata *cpudata = vcpu->cpudata;
1624 fakecr0 = cpudata->gprs[gpr];
1665 cpudata->gtlb_want_flush = true;
1678 struct vmx_cpudata *cpudata = vcpu->cpudata;
1692 gpr = cpudata->gprs[gpr];
1705 cpudata->gtlb_want_flush = true;
1717 struct vmx_cpudata *cpudata = vcpu->cpudata;
1735 cpudata->gcr8 = vmx_vmread(VMCS_GUEST_RSP);
1737 cpudata->gcr8 = cpudata->gprs[gpr];
1739 if (cpudata->tpr.exit_changed) {
1744 vmx_vmwrite(VMCS_GUEST_RSP, cpudata->gcr8);
1746 cpudata->gprs[gpr] = cpudata->gcr8;
1859 struct vmx_cpudata *cpudata = vcpu->cpudata;
1866 cpudata->gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF);
1867 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
1871 val = cpudata->gmsr_misc_enable;
1872 cpudata->gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF);
1873 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
1890 cpudata->gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF);
1891 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
1898 cpudata->gprs[NVMM_X64_GPR_RAX] = (val & 0xFFFFFFFF);
1899 cpudata->gprs[NVMM_X64_GPR_RDX] = (val >> 32);
1904 cpudata->gtsc = exit->u.wrmsr.val;
1905 cpudata->gtsc_want_update = true;
1942 struct vmx_cpudata *cpudata = vcpu->cpudata;
1946 exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
1964 struct vmx_cpudata *cpudata = vcpu->cpudata;
1967 rdx = cpudata->gprs[NVMM_X64_GPR_RDX];
1968 rax = cpudata->gprs[NVMM_X64_GPR_RAX];
1971 exit->u.wrmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
1990 struct vmx_cpudata *cpudata = vcpu->cpudata;
1995 val = (cpudata->gprs[NVMM_X64_GPR_RDX] << 32) |
1996 (cpudata->gprs[NVMM_X64_GPR_RAX] & 0xFFFFFFFF);
1998 if (__predict_false(cpudata->gprs[NVMM_X64_GPR_RCX] != 0)) {
2006 cpudata->gxcr0 = val;
2049 struct vmx_cpudata *cpudata = vcpu->cpudata;
2053 fpu_area_restore(&cpudata->gfpu, vmx_xcr0_mask, false);
2056 cpudata->hxcr0 = rdxcr(0);
2057 wrxcr(0, cpudata->gxcr0);
2064 struct vmx_cpudata *cpudata = vcpu->cpudata;
2067 cpudata->gxcr0 = rdxcr(0);
2068 wrxcr(0, cpudata->hxcr0);
2072 fpu_area_save(&cpudata->gfpu, vmx_xcr0_mask, false);
2079 struct vmx_cpudata *cpudata = vcpu->cpudata;
2085 ldr0(cpudata->drs[NVMM_X64_DR_DR0]);
2086 ldr1(cpudata->drs[NVMM_X64_DR_DR1]);
2087 ldr2(cpudata->drs[NVMM_X64_DR_DR2]);
2088 ldr3(cpudata->drs[NVMM_X64_DR_DR3]);
2089 ldr6(cpudata->drs[NVMM_X64_DR_DR6]);
2095 struct vmx_cpudata *cpudata = vcpu->cpudata;
2097 cpudata->drs[NVMM_X64_DR_DR0] = rdr0();
2098 cpudata->drs[NVMM_X64_DR_DR1] = rdr1();
2099 cpudata->drs[NVMM_X64_DR_DR2] = rdr2();
2100 cpudata->drs[NVMM_X64_DR_DR3] = rdr3();
2101 cpudata->drs[NVMM_X64_DR_DR6] = rdr6();
2109 struct vmx_cpudata *cpudata = vcpu->cpudata;
2117 cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE);
2123 struct vmx_cpudata *cpudata = vcpu->cpudata;
2125 wrmsr(MSR_STAR, cpudata->star);
2126 wrmsr(MSR_LSTAR, cpudata->lstar);
2127 wrmsr(MSR_CSTAR, cpudata->cstar);
2128 wrmsr(MSR_SFMASK, cpudata->sfmask);
2129 wrmsr(MSR_KERNELGSBASE, cpudata->kernelgsbase);
2145 struct vmx_cpudata *cpudata = vcpu->cpudata;
2148 cpudata->gtlb_want_flush = true;
2155 struct vmx_cpudata *cpudata = vcpu->cpudata;
2158 if (__predict_true(!kcpuset_isset(cpudata->htlb_want_flush, hcpu))) {
2165 kcpuset_clear(cpudata->htlb_want_flush, hcpu);
2169 vmx_htlb_flush(struct vmx_machdata *machdata, struct vmx_cpudata *cpudata)
2175 if (__predict_true(machgen == cpudata->vcpu_htlb_gen)) {
2179 kcpuset_copy(cpudata->htlb_want_flush, kcpuset_running);
2189 vmx_htlb_flush_ack(struct vmx_cpudata *cpudata, uint64_t machgen)
2191 cpudata->vcpu_htlb_gen = machgen;
2192 kcpuset_clear(cpudata->htlb_want_flush, cpu_number());
2196 vmx_exit_evt(struct vmx_cpudata *cpudata)
2200 cpudata->evt_pending = false;
2219 cpudata->evt_pending = true;
2228 struct vmx_cpudata *cpudata = vcpu->cpudata;
2249 launched = cpudata->vmcs_launched;
2259 cpudata->gtsc_want_update = true;
2267 if (cpudata->gtlb_want_flush) {
2268 vpid_desc.vpid = cpudata->asid;
2271 cpudata->gtlb_want_flush = false;
2274 if (__predict_false(cpudata->gtsc_want_update)) {
2275 vmx_vmwrite(VMCS_TSC_OFFSET, cpudata->gtsc - rdtsc());
2276 cpudata->gtsc_want_update = false;
2281 machgen = vmx_htlb_flush(machdata, cpudata);
2282 lcr2(cpudata->gcr2);
2284 ret = vmx_vmresume(cpudata->gprs);
2286 ret = vmx_vmlaunch(cpudata->gprs);
2288 cpudata->gcr2 = rcr2();
2289 vmx_htlb_flush_ack(cpudata, machgen);
2297 vmx_exit_evt(cpudata);
2383 cpudata->vmcs_launched = launched;
2385 cpudata->gtsc = vmx_vmread(VMCS_TSC_OFFSET) + rdtsc();
2391 exit->exitstate.cr8 = cpudata->gcr8;
2395 exit->exitstate.int_window_exiting = cpudata->int_window_exit;
2396 exit->exitstate.nmi_window_exiting = cpudata->nmi_window_exit;
2397 exit->exitstate.evt_pending = cpudata->evt_pending;
2583 struct vmx_cpudata *cpudata = vcpu->cpudata;
2593 cpudata->gtlb_want_flush = true;
2609 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs));
2611 memcpy(cpudata->gprs, state->gprs, sizeof(state->gprs));
2631 cpudata->gcr2 = state->crs[NVMM_X64_CR_CR2];
2640 cpudata->gcr8 = state->crs[NVMM_X64_CR_CR8];
2644 cpudata->gxcr0 = state->crs[NVMM_X64_CR_XCR0];
2645 cpudata->gxcr0 &= vmx_xcr0_mask;
2646 cpudata->gxcr0 |= XCR0_X87;
2650 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs));
2652 memcpy(cpudata->drs, state->drs, sizeof(state->drs));
2654 cpudata->drs[NVMM_X64_DR_DR6] &= 0xFFFFFFFF;
2655 vmx_vmwrite(VMCS_GUEST_DR7, cpudata->drs[NVMM_X64_DR_DR7]);
2659 cpudata->gmsr[VMX_MSRLIST_STAR].val =
2661 cpudata->gmsr[VMX_MSRLIST_LSTAR].val =
2663 cpudata->gmsr[VMX_MSRLIST_CSTAR].val =
2665 cpudata->gmsr[VMX_MSRLIST_SFMASK].val =
2667 cpudata->gmsr[VMX_MSRLIST_KERNELGSBASE].val =
2681 cpudata->gtsc = state->msrs[NVMM_X64_MSR_TSC];
2682 cpudata->gtsc_want_update = true;
2715 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu));
2717 memcpy(cpudata->gfpu.xsh_fxsave, &state->fpu,
2720 fpustate = (struct fxsave *)cpudata->gfpu.xsh_fxsave;
2726 cpudata->gfpu.xsh_xstate_bv = vmx_xcr0_mask;
2741 struct vmx_cpudata *cpudata = vcpu->cpudata;
2761 CTASSERT(sizeof(cpudata->gprs) == sizeof(state->gprs));
2763 memcpy(state->gprs, cpudata->gprs, sizeof(state->gprs));
2774 state->crs[NVMM_X64_CR_CR2] = cpudata->gcr2;
2777 state->crs[NVMM_X64_CR_CR8] = cpudata->gcr8;
2778 state->crs[NVMM_X64_CR_XCR0] = cpudata->gxcr0;
2784 CTASSERT(sizeof(cpudata->drs) == sizeof(state->drs));
2786 memcpy(state->drs, cpudata->drs, sizeof(state->drs));
2793 cpudata->gmsr[VMX_MSRLIST_STAR].val;
2795 cpudata->gmsr[VMX_MSRLIST_LSTAR].val;
2797 cpudata->gmsr[VMX_MSRLIST_CSTAR].val;
2799 cpudata->gmsr[VMX_MSRLIST_SFMASK].val;
2801 cpudata->gmsr[VMX_MSRLIST_KERNELGSBASE].val;
2812 state->msrs[NVMM_X64_MSR_TSC] = cpudata->gtsc;
2819 state->intr.int_window_exiting = cpudata->int_window_exit;
2820 state->intr.nmi_window_exiting = cpudata->nmi_window_exit;
2821 state->intr.evt_pending = cpudata->evt_pending;
2824 CTASSERT(sizeof(cpudata->gfpu.xsh_fxsave) == sizeof(state->fpu));
2826 memcpy(&state->fpu, cpudata->gfpu.xsh_fxsave,
2856 struct vmx_cpudata *cpudata = vcpu->cpudata;
2869 cpudata->asid = i;
2901 struct vmx_cpudata *cpudata = vcpu->cpudata;
2902 struct vmcs *vmcs = cpudata->vmcs;
2903 struct msr_entry *gmsr = cpudata->gmsr;
2926 memset(cpudata->msrbm, 0xFF, MSRBM_SIZE);
2927 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_EFER, true, true);
2928 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_STAR, true, true);
2929 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_LSTAR, true, true);
2930 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_CSTAR, true, true);
2931 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_SFMASK, true, true);
2932 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_KERNELGSBASE, true, true);
2933 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_CS, true, true);
2934 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_ESP, true, true);
2935 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_SYSENTER_EIP, true, true);
2936 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_FSBASE, true, true);
2937 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_GSBASE, true, true);
2938 vmx_vcpu_msr_allow(cpudata->msrbm, MSR_TSC, true, false);
2939 vmx_vmwrite(VMCS_MSR_BITMAP, (uint64_t)cpudata->msrbm_pa);
2957 vmx_vmwrite(VMCS_ENTRY_MSR_LOAD_ADDRESS, cpudata->gmsr_pa);
2958 vmx_vmwrite(VMCS_EXIT_MSR_STORE_ADDRESS, cpudata->gmsr_pa);
2996 cpudata->gmsr_misc_enable = rdmsr(MSR_MISC_ENABLE);
2997 cpudata->gmsr_misc_enable &=
2999 cpudata->gmsr_misc_enable |=
3003 cpudata->gfpu.xsh_xstate_bv = vmx_xcr0_mask;
3004 cpudata->gfpu.xsh_xcomp_bv = 0;
3007 cpudata->star = rdmsr(MSR_STAR);
3008 cpudata->lstar = rdmsr(MSR_LSTAR);
3009 cpudata->cstar = rdmsr(MSR_CSTAR);
3010 cpudata->sfmask = rdmsr(MSR_SFMASK);
3025 struct vmx_cpudata *cpudata;
3028 /* Allocate the VMX cpudata. */
3029 cpudata = (struct vmx_cpudata *)uvm_km_alloc(kernel_map,
3030 roundup(sizeof(*cpudata), PAGE_SIZE), 0,
3032 vcpu->cpudata = cpudata;
3035 error = vmx_memalloc(&cpudata->vmcs_pa, (vaddr_t *)&cpudata->vmcs,
3041 error = vmx_memalloc(&cpudata->msrbm_pa, (vaddr_t *)&cpudata->msrbm,
3047 error = vmx_memalloc(&cpudata->gmsr_pa, (vaddr_t *)&cpudata->gmsr, 1);
3051 kcpuset_create(&cpudata->htlb_want_flush, true);
3059 if (cpudata->vmcs_pa) {
3060 vmx_memfree(cpudata->vmcs_pa, (vaddr_t)cpudata->vmcs,
3063 if (cpudata->msrbm_pa) {
3064 vmx_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm,
3067 if (cpudata->gmsr_pa) {
3068 vmx_memfree(cpudata->gmsr_pa, (vaddr_t)cpudata->gmsr, 1);
3071 kmem_free(cpudata, sizeof(*cpudata));
3078 struct vmx_cpudata *cpudata = vcpu->cpudata;
3084 kcpuset_destroy(cpudata->htlb_want_flush);
3086 vmx_memfree(cpudata->vmcs_pa, (vaddr_t)cpudata->vmcs, VMCS_NPAGES);
3087 vmx_memfree(cpudata->msrbm_pa, (vaddr_t)cpudata->msrbm, MSRBM_NPAGES);
3088 vmx_memfree(cpudata->gmsr_pa, (vaddr_t)cpudata->gmsr, 1);
3089 uvm_km_free(kernel_map, (vaddr_t)cpudata,
3090 roundup(sizeof(*cpudata), PAGE_SIZE), UVM_KMF_WIRED);
3096 vmx_vcpu_configure_cpuid(struct vmx_cpudata *cpudata, void *data)
3115 if (!cpudata->cpuidpresent[i]) {
3118 if (cpudata->cpuid[i].leaf == cpuid->leaf) {
3119 cpudata->cpuidpresent[i] = false;
3127 if (!cpudata->cpuidpresent[i]) {
3130 if (cpudata->cpuid[i].leaf == cpuid->leaf) {
3131 memcpy(&cpudata->cpuid[i], cpuid,
3139 if (!cpudata->cpuidpresent[i]) {
3140 cpudata->cpuidpresent[i] = true;
3141 memcpy(&cpudata->cpuid[i], cpuid,
3151 vmx_vcpu_configure_tpr(struct vmx_cpudata *cpudata, void *data)
3155 memcpy(&cpudata->tpr, tpr, sizeof(*tpr));
3162 struct vmx_cpudata *cpudata = vcpu->cpudata;
3166 return vmx_vcpu_configure_cpuid(cpudata, data);
3168 return vmx_vcpu_configure_tpr(cpudata, data);
3177 struct vmx_cpudata *cpudata = vcpu->cpudata;
3180 KASSERT(cpudata->vmcs_refcnt == 0);
3182 vmcs_ci = cpudata->vmcs_ci;
3183 cpudata->vmcs_ci = (void *)0x00FFFFFFFFFFFFFF; /* clobber */
3190 vmx_vmclear_remote(vmcs_ci, cpudata->vmcs_pa);
3193 vmx_vmclear(&cpudata->vmcs_pa);
3201 struct vmx_cpudata *cpudata = vcpu->cpudata;
3203 KASSERT(cpudata->vmcs_refcnt == 0);
3206 cpudata->vmcs_ci = NULL;
Indexes created Mon Oct 13 05:10:05 GMT 2025