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Lines Matching refs:rdmsr

906 	msr = rdmsr(MSR_IA32_VMX_BASIC);
1864 		if (exit->u.rdmsr.msr == MSR_CR_PAT) {
1870 		if (exit->u.rdmsr.msr == MSR_MISC_ENABLE) {
1876 		if (exit->u.rdmsr.msr == MSR_IA32_ARCH_CAPABILITIES) {
1885 			val = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
1895 			if (msr_ignore_list[i] != exit->u.rdmsr.msr)
1946 	exit->u.rdmsr.msr = (cpudata->gprs[NVMM_X64_GPR_RCX] & 0xFFFFFFFF);
1955 	exit->u.rdmsr.npc = rip + inslen;
2113 	vmx_vmwrite(VMCS_HOST_FS_BASE, rdmsr(MSR_FSBASE));
2117 	cpudata->kernelgsbase = rdmsr(MSR_KERNELGSBASE);
2258 		vmx_vmwrite(VMCS_HOST_GS_BASE, rdmsr(MSR_GSBASE));
2980 	vmx_vmwrite(VMCS_HOST_IA32_PAT, rdmsr(MSR_CR_PAT));
2981 	vmx_vmwrite(VMCS_HOST_IA32_EFER, rdmsr(MSR_EFER));
2996 	cpudata->gmsr_misc_enable = rdmsr(MSR_MISC_ENABLE);
3007 	cpudata->star = rdmsr(MSR_STAR);
3008 	cpudata->lstar = rdmsr(MSR_LSTAR);
3009 	cpudata->cstar = rdmsr(MSR_CSTAR);
3010 	cpudata->sfmask = rdmsr(MSR_SFMASK);
3271 	basic = rdmsr(MSR_IA32_VMX_BASIC);
3274 	val = rdmsr(msr_ctls);
3276 		true_val = rdmsr(msr_true_ctls);
3301 	basic = rdmsr(MSR_IA32_VMX_BASIC);
3304 	val = rdmsr(msr_ctls);
3306 		true_val = rdmsr(msr_true_ctls);
3353 	msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
3360 	msr = rdmsr(MSR_IA32_VMX_BASIC);
3371 	vmx_cr0_fixed0 = rdmsr(MSR_IA32_VMX_CR0_FIXED0) & ~(CR0_PG|CR0_PE);
3372 	vmx_cr0_fixed1 = rdmsr(MSR_IA32_VMX_CR0_FIXED1) | (CR0_PG|CR0_PE);
3379 	vmx_cr4_fixed0 = rdmsr(MSR_IA32_VMX_CR4_FIXED0);
3380 	vmx_cr4_fixed1 = rdmsr(MSR_IA32_VMX_CR4_FIXED1);
3435 	msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
3484 		msr = rdmsr(MSR_IA32_FEATURE_CONTROL);
3523 		msr = rdmsr(MSR_IA32_ARCH_CAPABILITIES);
3593 	msr = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);