Cross Reference: /src/sys/dev/pci/artsata.c

Lines Matching refs:sc_wdcdev
113 	sc->sc_wdcdev.sc_atac.atac_dev = self;
136 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
144 		    device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
146 			aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
149 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
162 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
170 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
181 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
196 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
204 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
212 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
234 	cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
247 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
272 	sc->sc_wdcdev.dma_arg = sc;
273 	sc->sc_wdcdev.dma_init = pciide_dma_init;
274 	sc->sc_wdcdev.dma_start = pciide_dma_start;
275 	sc->sc_wdcdev.dma_finish = pciide_dma_finish;
279 	if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
321 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
330 	sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS;
332 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
333 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
335 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
336 		sc->sc_wdcdev.irqack = pciide_irqack;
337 		sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
338 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
340 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
342 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
343 	sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN;
344 	sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
345 	sc->sc_wdcdev.wdc_maxdrives = 1;
347 	wdc_allocate_regs(&sc->sc_wdcdev);
360 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
370 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
397 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
413 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
414 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
416 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
417 		sc->sc_wdcdev.irqack = pciide_irqack;
418 		sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
419 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
421 	sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
423 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
424 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
426 	wdc_allocate_regs(&sc->sc_wdcdev);
428 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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