Cross Reference: /src/sys/dev/pci/cmdide.c

Lines Matching refs:sc_wdcdev
121 	sc->sc_wdcdev.sc_atac.atac_dev = self;
155 	cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
159 		sc->sc_wdcdev.sc_atac.atac_claim_hw = cmd064x_claim_hw;
160 		sc->sc_wdcdev.sc_atac.atac_free_hw  = cmd064x_free_hw;
164 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
178 		aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
213 	for(uint i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
238 	for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
250 				      sc->sc_wdcdev.sc_atac.atac_dev), i);
278 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
282 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
283 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
284 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16;
285 	sc->sc_wdcdev.wdc_maxdrives = 2;
287 	wdc_allocate_regs(&sc->sc_wdcdev);
289 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
316 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
320 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
322 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
325 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
326 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
327 			sc->sc_wdcdev.irqack = cmd646_9_irqack;
330 			sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
331 			sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
332 			sc->sc_wdcdev.irqack = cmd646_9_irqack;
336 				sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
337 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
345 				sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
346 				sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
354 			sc->sc_wdcdev.irqack = cmd646_9_irqack;
357 			sc->sc_wdcdev.irqack = pciide_irqack;
361 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
362 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
363 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
364 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
365 	sc->sc_wdcdev.sc_atac.atac_set_modes = cmd0643_9_setup_channel;
366 	sc->sc_wdcdev.wdc_maxdrives = 2;
373 	wdc_allocate_regs(&sc->sc_wdcdev);
375 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
426 				else if (sc->sc_wdcdev.sc_atac.atac_udma_cap > 2)
443 				if (sc->sc_wdcdev.sc_atac.atac_cap & ATAC_CAP_UDMA) {
494 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
498 	sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
500 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
501 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
502 		sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
503 		sc->sc_wdcdev.irqack = pciide_irqack;
506 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
507 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
508 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
509 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
510 	sc->sc_wdcdev.sc_atac.atac_set_modes = cmd680_setup_channel;
511 	sc->sc_wdcdev.wdc_maxdrives = 2;
518 	wdc_allocate_regs(&sc->sc_wdcdev);
520 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
547 	cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
554 	aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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