Cross Reference: /src/sys/dev/pci/cs4281.c

Lines Matching refs:BA0READ4
317 	intr = BA0READ4(sc, CS4281_HISR);
329 		hdsr0 = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */
331 		hdsr1 = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */
348 				(int)BA0READ4(sc, CS4281_DCA0),
349 				(int)BA0READ4(sc, CS4281_DCC0)));
369 			DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1),
370 				(int)BA0READ4(sc, CS4281_DCC1)));
420 	BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
431 	BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
468 	BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
507 	fmt = BA0READ4(sc, CS4281_DMR0) & ~DMRn_FMTMSK;
517 	BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) & ~DCRn_MSK);
521 	DPRINTF(("HICR =0x%08x(expected 0x00000001)\n", BA0READ4(sc, CS4281_HICR)));
522 	DPRINTF(("HIMR =0x%08x(expected 0x00f0fc3f)\n", BA0READ4(sc, CS4281_HIMR)));
523 	DPRINTF(("DMR0 =0x%08x(expected 0x2???0018)\n", BA0READ4(sc, CS4281_DMR0)));
524 	DPRINTF(("DCR0 =0x%08x(expected 0x00030000)\n", BA0READ4(sc, CS4281_DCR0)));
525 	DPRINTF(("FCR0 =0x%08x(expected 0x81000f00)\n", BA0READ4(sc, CS4281_FCR0)));
527 		 BA0READ4(sc, CS4281_DACSR)));
528 	DPRINTF(("SRCSA=0x%08x(expected 0x0b0a0100)\n", BA0READ4(sc, CS4281_SRCSA)));
530 		 BA0READ4(sc, CS4281_SSPM) & SSPM_PSRCEN));
558 	BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
587 	fmt = BA0READ4(sc, CS4281_DMR1) & ~DMRn_FMTMSK;
597 	BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) & ~DCRn_MSK);
601 	DPRINTF(("HICR=0x%08x\n", BA0READ4(sc, CS4281_HICR)));
602 	DPRINTF(("HIMR=0x%08x\n", BA0READ4(sc, CS4281_HIMR)));
603 	DPRINTF(("DMR1=0x%08x\n", BA0READ4(sc, CS4281_DMR1)));
604 	DPRINTF(("DCR1=0x%08x\n", BA0READ4(sc, CS4281_DCR1)));
619 		sc->sc_suspend_state.cs4281.dcr0 = BA0READ4(sc, CS4281_DCR0);
620 		sc->sc_suspend_state.cs4281.dmr0 = BA0READ4(sc, CS4281_DMR0);
621 		sc->sc_suspend_state.cs4281.dbc0 = BA0READ4(sc, CS4281_DBC0);
622 		sc->sc_suspend_state.cs4281.dba0 = BA0READ4(sc, CS4281_DBA0);
627 		sc->sc_suspend_state.cs4281.dcr1 = BA0READ4(sc, CS4281_DCR1);
628 		sc->sc_suspend_state.cs4281.dmr1 = BA0READ4(sc, CS4281_DMR1);
629 		sc->sc_suspend_state.cs4281.dbc1 = BA0READ4(sc, CS4281_DBC1);
630 		sc->sc_suspend_state.cs4281.dba1 = BA0READ4(sc, CS4281_DBA1);
633 	BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
634 	BA0WRITE4(sc, CS4281_DCR1, BA0READ4(sc, CS4281_DCR1) | DCRn_MSK);
714 	while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) {
724 	while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) {
743 		dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY;
774 		dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4) ;
851 	dat32 = BA0READ4(sc, CS4281_EPPMC);
893 	while ((BA0READ4(sc, CS4281_CLKCR1) & (CLKCR1_DLLRDY | CLKCR1_CLKON))
904 	while (!(BA0READ4(sc, CS4281_CLKCR1) & CLKCR1_DLLRDY)) {
919 	while ((BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY) == 0) {
931 	while ((BA0READ4(sc, CS4281_ACSTS2) & ACSTS2_CRDY2) == 0) {
954 		dat32 = BA0READ4(sc, CS428X_ACSTS) & ACSTS_CRDY;
985 		dat32 = BA0READ4(sc, CS428X_ACISV) & (ACISV_ISV3 | ACISV_ISV4);
1025 	mem = BA0READ4(sc, CS4281_SERMC);
1046 	BA0WRITE4(sc, CS4281_FCR0, (BA0READ4(sc, CS4281_FCR0) & ~FCRn_FEN));
1067 	BA0WRITE4(sc, CS4281_FCR1, (BA0READ4(sc, CS4281_FCR1) & ~FCRn_FEN));
1090 	BA0WRITE4(sc, CS4281_FCR2, (BA0READ4(sc, CS4281_FCR2) & ~FCRn_FEN));
1091 	BA0WRITE4(sc, CS4281_FCR3, (BA0READ4(sc, CS4281_FCR3) & ~FCRn_FEN));
1142 		  BA0READ4(sc, CS4281_HIMR) & dat32);
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