Cross Reference: /src/sys/dev/pci/cxgb/cxgb

Lines Matching refs:MDIO_DEV_PMA_PMD
64     err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_DISABLE, !!enable);
66         err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
76         (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL100X_TX_CONFIG1, 1)) ||
77         (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_HI, 0)) ||
78         (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_PWR_DOWN_LO, 0)) ||
79         (err = mdio_write(phy, MDIO_DEV_PMA_PMD, AEL1002_XFI_EQL, 0x18)) ||
80         (err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, AEL1002_LB_EN,
96         int err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &status);
103             err = mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR,
153     return t3_phy_reset(phy, MDIO_DEV_PMA_PMD, wait);
158     return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 1);
163     return mdio_write(phy, MDIO_DEV_PMA_PMD, LASI_CTRL, 0);
170     return mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &val);
176     int err = mdio_read(phy, MDIO_DEV_PMA_PMD, LASI_STAT, &status);
185     return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
263     if (!phy_addr && !mdio_read(phy, MDIO_DEV_PMA_PMD, MII_BMSR, &stat) &&
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