Cross Reference: /src/sys/dev/pci/cxgb/cxgb

Lines Matching defs:adapter
99 static int mc5_cmd_write(adapter_t *adapter, u32 cmd)
101     t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_CMD, cmd);
102     return t3_wait_op_done(adapter, A_MC5_DB_DBGI_RSP_STATUS,
106 static inline void dbgi_wr_addr3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
108     t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, v1);
109     t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR1, v2);
110     t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR2, v3);
113 static inline void dbgi_wr_data3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
115     t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA0, v1);
116     t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA1, v2);
117     t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA2, v3);
120 static inline void dbgi_rd_rsp3(adapter_t *adapter, u32 *v1, u32 *v2, u32 *v3)
122     *v1 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA0);
123     *v2 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA1);
124     *v3 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA2);
132 static int mc5_write(adapter_t *adapter, u32 addr_lo, u32 cmd)
134     t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, addr_lo);
135     if (mc5_cmd_write(adapter, cmd) == 0)
137     CH_ERR(adapter, "MC5 timeout writing to TCAM address 0x%x\n", addr_lo);
146     adapter_t *adap = mc5->adapter;
194     adapter_t *adap = mc5->adapter;
258     adapter_t *adap = mc5->adapter;
318     t3_set_reg_field(mc5->adapter, A_MC5_DB_CONFIG, F_PRTYEN | F_MBUSEN,
325     t3_set_reg_field(mc5->adapter, A_MC5_DB_CONFIG, F_DBGIEN,
339     adapter_t *adap = mc5->adapter;
401     adapter_t *adap = mc5->adapter;
433     adapter_t *adap = mc5->adapter;
465 void __devinit t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode)
475     u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG);
477     mc5->adapter = adapter;