Cross Reference: /src/sys/dev/pci/cxgb/cxgb

Lines Matching defs:cphy
141 static int mv88e1xxx_reset(struct cphy *cphy, int wait)
143     return t3_phy_reset(cphy, 0, wait);
146 static int mv88e1xxx_intr_enable(struct cphy *cphy)
148     return mdio_write(cphy, 0, MV88E1XXX_INTR_ENABLE, INTR_ENABLE_MASK);
151 static int mv88e1xxx_intr_disable(struct cphy *cphy)
153     return mdio_write(cphy, 0, MV88E1XXX_INTR_ENABLE, 0);
156 static int mv88e1xxx_intr_clear(struct cphy *cphy)
161     return mdio_read(cphy, 0, MV88E1XXX_INTR_STATUS, &val);
164 static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover)
166     return t3_mdio_change_bits(cphy, 0, MV88E1XXX_SPECIFIC_CNTRL,
171 static int mv88e1xxx_autoneg_enable(struct cphy *cphy)
173     mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO);
176     return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
180 static int mv88e1xxx_autoneg_restart(struct cphy *cphy)
182     return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
186 static int mv88e1xxx_set_loopback(struct cphy *cphy, int mmd, int dir, int on)
188     return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_LOOPBACK,
192 static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_ok,
198     mdio_read(cphy, 0, MV88E1XXX_SPECIFIC_STATUS, &status);
224 static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable)
230     return t3_mdio_change_bits(cphy, 0, MV88E1XXX_EXT_SPECIFIC_CNTRL,
235 static int mv88e1xxx_power_down(struct cphy *cphy, int enable)
237     return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN,
241 static int mv88e1xxx_intr_handler(struct cphy *cphy)
250     mdio_read(cphy, 0, MV88E1XXX_INTR_STATUS, &cause);
292 void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,