Lines Matching defs:adapter
45 * @adapter: the adapter performing the operation
58 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
62 u32 val = t3_read_reg(adapter, reg);
78 * @adapter: the adapter to program
87 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
91 t3_write_reg(adapter, p->reg_addr + offset, p->val);
98 * @adapter: the adapter to program
106 void t3_set_reg_field(adapter_t *adapter, unsigned int addr, u32 mask, u32 val)
108 u32 v = t3_read_reg(adapter, addr) & ~mask;
110 t3_write_reg(adapter, addr, v | val);
111 (void) t3_read_reg(adapter, addr); /* flush */
116 * @adap: the adapter
154 adapter_t *adap = mc7->adapter;
214 static int mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr,
223 MDIO_LOCK(adapter);
224 t3_write_reg(adapter, A_MI1_ADDR, addr);
225 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
226 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
228 *valp = t3_read_reg(adapter, A_MI1_DATA);
229 MDIO_UNLOCK(adapter);
233 static int mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr,
242 MDIO_LOCK(adapter);
243 t3_write_reg(adapter, A_MI1_ADDR, addr);
244 t3_write_reg(adapter, A_MI1_DATA, val);
245 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
246 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
247 MDIO_UNLOCK(adapter);
259 static int mi1_ext_read(adapter_t *adapter, int phy_addr, int mmd_addr,
265 MDIO_LOCK(adapter);
266 t3_write_reg(adapter, A_MI1_ADDR, addr);
267 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
268 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
269 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
271 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3));
272 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
275 *valp = t3_read_reg(adapter, A_MI1_DATA);
277 MDIO_UNLOCK(adapter);
281 static int mi1_ext_write(adapter_t *adapter, int phy_addr, int mmd_addr,
287 MDIO_LOCK(adapter);
288 t3_write_reg(adapter, A_MI1_ADDR, addr);
289 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
290 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
291 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0, MDIO_ATTEMPTS, 10);
293 t3_write_reg(adapter, A_MI1_DATA, val);
294 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
295 ret = t3_wait_op_done(adapter, A_MI1_OP, F_BUSY, 0,
298 MDIO_UNLOCK(adapter);
540 * @adapter: adapter to read
549 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data)
553 unsigned int base = adapter->params.pci.vpd_cap_addr;
558 t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR, (u16)addr);
561 t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val);
565 CH_ERR(adapter, "reading EEPROM address 0x%x failed\n", addr);
568 t3_os_pci_read_config_4(adapter, base + PCI_VPD_DATA, data);
575 * @adapter: adapter to write
582 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data)
586 unsigned int base = adapter->params.pci.vpd_cap_addr;
591 t3_os_pci_write_config_4(adapter, base + PCI_VPD_DATA,
593 t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR,
597 t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val);
601 CH_ERR(adapter, "write to EEPROM address 0x%x failed\n", addr);
609 * @adapter: the adapter
614 int t3_seeprom_wp(adapter_t *adapter, int enable)
616 return t3_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
629 * @adapter: adapter to read
634 static int get_vpd_params(adapter_t *adapter, struct vpd_params *p)
643 ret = t3_seeprom_read(adapter, VPD_BASE, (u32 *)&vpd);
649 ret = t3_seeprom_read(adapter, addr + i,
663 if (adapter->params.rev == 0 && !vpd.port0_data[0]) {
664 p->port_type[0] = uses_xaui(adapter) ? 1 : 2;
665 p->port_type[1] = uses_xaui(adapter) ? 6 : 2;
702 * @adapter: the adapter
711 static int sf1_read(adapter_t *adapter, unsigned int byte_cnt, int cont,
718 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
720 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
721 ret = t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
723 *valp = t3_read_reg(adapter, A_SF_DATA);
729 * @adapter: the adapter
738 static int sf1_write(adapter_t *adapter, unsigned int byte_cnt, int cont,
743 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
745 t3_write_reg(adapter, A_SF_DATA, val);
746 t3_write_reg(adapter, A_SF_OP,
748 return t3_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 10);
753 * @adapter: the adapter
759 static int flash_wait_op(adapter_t *adapter, int attempts, int delay)
765 if ((ret = sf1_write(adapter, 1, 1, SF_RD_STATUS)) != 0 ||
766 (ret = sf1_read(adapter, 1, 0, &status)) != 0)
779 * @adapter: the adapter
790 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
800 if ((ret = sf1_write(adapter, 4, 1, addr)) != 0 ||
801 (ret = sf1_read(adapter, 1, 1, data)) != 0)
805 ret = sf1_read(adapter, 4, nwords > 1, data);
816 * @adapter: the adapter
824 static int t3_write_flash(adapter_t *adapter, unsigned int addr,
836 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
837 (ret = sf1_write(adapter, 4, 1, val)) != 0)
845 ret = sf1_write(adapter, c, c != left, val);
849 if ((ret = flash_wait_op(adapter, 5, 1)) != 0)
853 ret = t3_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
864 * @adapter: the adapter
869 int t3_get_tp_version(adapter_t *adapter, u32 *vers)
874 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
875 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0,
880 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
887 * @adapter: the adapter
890 int t3_check_tpsram_version(adapter_t *adapter)
897 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
898 ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0,
903 vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
911 CH_WARN(adapter, "found wrong TP version (%u.%u), "
920 * @adapter: the adapter
924 * Checks if an adapter's tp sram is compatible with the driver.
927 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_sram, unsigned int size)
937 CH_ERR(adapter, "corrupted protocol SRAM image, checksum %u\n",
952 * @adapter: the adapter
957 int t3_get_fw_version(adapter_t *adapter, u32 *vers)
959 return t3_read_flash(adapter, FW_VERS_ADDR, 1, vers, 0);
964 * @adapter: the adapter
966 * Checks if an adapter's FW is compatible with the driver. Returns 0
969 int t3_check_fw_version(adapter_t *adapter)
975 ret = t3_get_fw_version(adapter, &vers);
987 CH_WARN(adapter, "found wrong FW version (%u.%u), "
995 * @adapter: the adapter
1001 static int t3_flash_erase_sectors(adapter_t *adapter, int start, int end)
1006 if ((ret = sf1_write(adapter, 1, 0, SF_WR_ENABLE)) != 0 ||
1007 (ret = sf1_write(adapter, 4, 0,
1009 (ret = flash_wait_op(adapter, 5, 500)) != 0)
1018 * @adapter: the adapter
1027 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size)
1042 CH_ERR(adapter, "corrupted firmware image, checksum %u\n",
1047 ret = t3_flash_erase_sectors(adapter, fw_sector, fw_sector);
1055 ret = t3_write_flash(adapter, addr, chunk_size, fw_data);
1064 ret = t3_write_flash(adapter, FW_VERS_ADDR, 4, fw_data);
1067 CH_ERR(adapter, "firmware download failed, error %d\n", ret);
1075 * @adap: the adapter
1102 * @adapter: the adapter
1109 void t3_link_changed(adapter_t *adapter, int port_id)
1112 struct port_info *pi = adap2pinfo(adapter, port_id);
1119 if (link_ok != lc->link_ok && adapter->params.rev > 0 &&
1120 uses_xaui(adapter)) {
1123 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1140 t3_os_link_changed(adapter, port_id, link_ok, speed, duplex, fc);
1191 * @adapter: the adapter
1192 * @ports: bitmap of adapter ports to operate on
1197 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on)
1199 t3_set_reg_field(adapter, A_TP_OUT_CONFIG,
1213 * @adapter: the adapter that generated the interrupt
1226 static int t3_handle_intr_status(adapter_t *adapter, unsigned int reg,
1232 unsigned int status = t3_read_reg(adapter, reg) & mask;
1238 CH_ALERT(adapter, "%s (0x%x)\n",
1241 CH_WARN(adapter, "%s (0x%x)\n",
1247 t3_write_reg(adapter, reg, status);
1296 static void pci_intr_handler(adapter_t *adapter)
1324 if (t3_handle_intr_status(adapter, A_PCIX_INT_CAUSE, PCIX_INTR_MASK,
1325 pcix1_intr_info, adapter->irq_stats))
1326 t3_fatal_err(adapter);
1332 static void pcie_intr_handler(adapter_t *adapter)
1350 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR)
1351 CH_ALERT(adapter, "PEX error code 0x%x\n",
1352 t3_read_reg(adapter, A_PCIE_PEX_ERR));
1354 if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK,
1355 pcie_intr_info, adapter->irq_stats))
1356 t3_fatal_err(adapter);
1362 static void tp_intr_handler(adapter_t *adapter)
1371 if (t3_handle_intr_status(adapter, A_TP_INT_CAUSE, 0xffffffff,
1373 t3_fatal_err(adapter);
1379 static void cim_intr_handler(adapter_t *adapter)
1397 if (t3_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 0xffffffff,
1399 t3_fatal_err(adapter);
1405 static void ulprx_intr_handler(adapter_t *adapter)
1412 if (t3_handle_intr_status(adapter, A_ULPRX_INT_CAUSE, 0xffffffff,
1414 t3_fatal_err(adapter);
1420 static void ulptx_intr_handler(adapter_t *adapter)
1430 if (t3_handle_intr_status(adapter, A_ULPTX_INT_CAUSE, 0xffffffff,
1431 ulptx_intr_info, adapter->irq_stats))
1432 t3_fatal_err(adapter);
1447 static void pmtx_intr_handler(adapter_t *adapter)
1460 if (t3_handle_intr_status(adapter, A_PM1_TX_INT_CAUSE, 0xffffffff,
1462 t3_fatal_err(adapter);
1477 static void pmrx_intr_handler(adapter_t *adapter)
1490 if (t3_handle_intr_status(adapter, A_PM1_RX_INT_CAUSE, 0xffffffff,
1492 t3_fatal_err(adapter);
1498 static void cplsw_intr_handler(adapter_t *adapter)
1509 if (t3_handle_intr_status(adapter, A_CPL_INTR_CAUSE, 0xffffffff,
1511 t3_fatal_err(adapter);
1517 static void mps_intr_handler(adapter_t *adapter)
1524 if (t3_handle_intr_status(adapter, A_MPS_INT_CAUSE, 0xffffffff,
1526 t3_fatal_err(adapter);
1536 adapter_t *adapter = mc7->adapter;
1537 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
1541 CH_WARN(adapter, "%s MC7 correctable error at addr 0x%x, "
1543 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
1544 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
1545 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
1546 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
1551 CH_ALERT(adapter, "%s MC7 uncorrectable error at addr 0x%x, "
1553 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
1554 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
1555 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
1556 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
1561 CH_ALERT(adapter, "%s MC7 parity error 0x%x\n",
1568 if (adapter->params.rev > 0)
1569 addr = t3_read_reg(adapter,
1572 CH_ALERT(adapter, "%s MC7 address error: 0x%x\n",
1577 t3_fatal_err(adapter);
1579 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
1624 int t3_phy_intr_handler(adapter_t *adapter)
1626 u32 mask, gpi = adapter_info(adapter)->gpio_intr;
1627 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1629 for_each_port(adapter, i) {
1630 struct port_info *p = adap2pinfo(adapter, i);
1642 t3_link_changed(adapter, i);
1648 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause);
1654 * @adapter: the adapter
1660 int t3_slow_intr_handler(adapter_t *adapter)
1662 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);
1664 cause &= adapter->slow_intr_mask;
1668 if (is_pcie(adapter))
1669 pcie_intr_handler(adapter);
1671 pci_intr_handler(adapter);
1674 t3_sge_err_intr_handler(adapter);
1676 mc7_intr_handler(&adapter->pmrx);
1678 mc7_intr_handler(&adapter->pmtx);
1680 mc7_intr_handler(&adapter->cm);
1682 cim_intr_handler(adapter);
1684 tp_intr_handler(adapter);
1686 ulprx_intr_handler(adapter);
1688 ulptx_intr_handler(adapter);
1690 pmrx_intr_handler(adapter);
1692 pmtx_intr_handler(adapter);
1694 cplsw_intr_handler(adapter);
1696 mps_intr_handler(adapter);
1698 t3_mc5_intr_handler(&adapter->mc5);
1700 mac_intr_handler(adapter, 0);
1702 mac_intr_handler(adapter, 1);
1704 t3_os_ext_intr_handler(adapter);
1707 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
1708 (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1714 * @adapter: the adapter whose interrupts should be enabled
1720 void t3_intr_enable(adapter_t *adapter)
1738 adapter->slow_intr_mask = PL_INTR_MASK;
1740 t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0);
1742 if (adapter->params.rev > 0) {
1743 t3_write_reg(adapter, A_CPL_INTR_ENABLE,
1745 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1749 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
1750 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
1753 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW,
1754 adapter_info(adapter)->gpio_intr);
1755 t3_write_reg(adapter, A_T3DBG_INT_ENABLE,
1756 adapter_info(adapter)->gpio_intr);
1757 if (is_pcie(adapter))
1758 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
1760 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
1761 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
1762 (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1767 * @adapter: the adapter whose interrupts should be disabled
1772 void t3_intr_disable(adapter_t *adapter)
1774 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0);
1775 (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1776 adapter->slow_intr_mask = 0;
1781 * @adapter: the adapter whose interrupts should be cleared
1785 void t3_intr_clear(adapter_t *adapter)
1808 for_each_port(adapter, i)
1809 t3_port_intr_clear(adapter, i);
1812 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff);
1814 if (is_pcie(adapter))
1815 t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff);
1816 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff);
1817 (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1822 * @adapter: associated adapter
1826 * adapter port.
1828 void t3_port_intr_enable(adapter_t *adapter, int idx)
1830 struct port_info *pi = adap2pinfo(adapter, idx);
1832 t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, XGM_INTR_MASK);
1838 * @adapter: associated adapter
1842 * adapter port.
1844 void t3_port_intr_disable(adapter_t *adapter, int idx)
1846 struct port_info *pi = adap2pinfo(adapter, idx);
1848 t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, 0);
1854 * @adapter: associated adapter
1858 * adapter port.
1860 void t3_port_intr_clear(adapter_t *adapter, int idx)
1862 struct port_info *pi = adap2pinfo(adapter, idx);
1864 t3_write_reg(adapter, A_XGM_INT_CAUSE + pi->mac.offset, 0xffffffff);
1872 * @adapter: the adapter
1879 static int t3_sge_write_context(adapter_t *adapter, unsigned int id,
1882 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
1883 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
1884 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
1885 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
1886 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
1888 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
1894 * @adapter: the adapter to configure
1909 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
1918 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1922 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) |
1924 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) |
1927 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, (u32)base_addr);
1929 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
1933 return t3_sge_write_context(adapter, id, F_EGRESS);
1938 * @adapter: the adapter to configure
1952 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
1958 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1962 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, (u32)base_addr);
1964 t3_write_reg(adapter, A_SG_CONTEXT_DATA1,
1967 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) |
1970 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
1973 return t3_sge_write_context(adapter, id, F_FREELIST);
1978 * @adapter: the adapter to configure
1991 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
1999 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2003 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) |
2005 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr);
2009 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2011 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres);
2012 return t3_sge_write_context(adapter, id, F_RESPONSEQ);
2017 * @adapter: the adapter to configure
2030 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
2036 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2040 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size));
2041 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr);
2043 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2047 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
2049 return t3_sge_write_context(adapter, id, F_CQ);
2054 * @adapter: the adapter
2061 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable)
2063 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2066 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2067 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2068 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2069 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID);
2070 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable));
2071 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2073 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2079 * @adapter: the adapter
2085 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id)
2087 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2090 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2091 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2092 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE));
2093 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2094 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0);
2095 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2097 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2103 * @adapter: the adapter
2109 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id)
2111 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2114 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2115 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2116 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2117 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2118 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2119 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2121 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2127 * @adapter: the adapter
2133 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id)
2135 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2138 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2139 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2140 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2141 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2142 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2143 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2145 return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2151 * @adapter: the adapter
2163 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
2168 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2171 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16);
2172 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) |
2174 if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
2179 if (adapter->params.rev > 0)
2182 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2184 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD,
2188 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0));
2196 * @adapter: the adapter
2203 static int t3_sge_read_context(unsigned int type, adapter_t *adapter,
2206 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2209 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2211 if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0,
2214 data[0] = t3_read_reg(adapter, A_SG_CONTEXT_DATA0);
2215 data[1] = t3_read_reg(adapter, A_SG_CONTEXT_DATA1);
2216 data[2] = t3_read_reg(adapter, A_SG_CONTEXT_DATA2);
2217 data[3] = t3_read_reg(adapter, A_SG_CONTEXT_DATA3);
2223 * @adapter: the adapter
2230 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4])
2234 return t3_sge_read_context(F_EGRESS, adapter, id, data);
2239 * @adapter: the adapter
2246 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4])
2250 return t3_sge_read_context(F_CQ, adapter, id, data);
2255 * @adapter: the adapter
2262 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4])
2266 return t3_sge_read_context(F_FREELIST, adapter, id, data);
2271 * @adapter: the adapter
2278 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4])
2282 return t3_sge_read_context(F_RESPONSEQ, adapter, id, data);
2287 * @adapter: the adapter
2297 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
2311 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val);
2316 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2322 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config);
2327 * @adapter: the adapter
2333 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map)
2340 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE,
2342 val = t3_read_reg(adapter, A_TP_RSS_LKP_TABLE);
2351 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2353 val = t3_read_reg(adapter, A_TP_RSS_MAP_TABLE);
2363 * @adap: the adapter
2377 * @adap: the adapter
2394 * @adap: the adapter
2461 * @adap: the adapter
2595 * @adap: the adapter to set
2641 * @adap: the adapter
2671 * @adap: the adapter
2757 * @adap: the adapter
2801 * @adap: the adapter
2821 * @adap: the adapter
2843 * @adap: the adapter
2856 * @adap: the adapter
2873 * @adap: the adapter
2918 * @adapter: the adapter
2945 * @adapter: the adapter
2953 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
2974 tp_wr_indirect(adapter, addr++, key[0]);
2975 tp_wr_indirect(adapter, addr++, mask[0]);
2976 tp_wr_indirect(adapter, addr++, key[1]);
2977 tp_wr_indirect(adapter, addr++, mask[1]);
2978 tp_wr_indirect(adapter, addr++, key[2]);
2979 tp_wr_indirect(adapter, addr++, mask[2]);
2980 tp_wr_indirect(adapter, addr++, key[3]);
2981 tp_wr_indirect(adapter, addr, mask[3]);
2982 (void) t3_read_reg(adapter, A_TP_PIO_DATA);
2987 * @adap: the adapter
3031 * @adap: the adapter
3060 * @adap: the adapter
3100 * @adap: the adapter
3128 * @adap: the adapter
3144 * @adap: the adapter
3187 static int calibrate_xgm(adapter_t *adapter)
3189 if (uses_xaui(adapter)) {
3193 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
3194 (void) t3_read_reg(adapter, A_XGM_XAUI_IMP);
3196 v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
3198 t3_write_reg(adapter, A_XGM_XAUI_IMP,
3203 CH_ERR(adapter, "MAC calibration failed\n");
3206 t3_write_reg(adapter, A_XGM_RGMII_IMP,
3208 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
3214 static void calibrate_xgm_t3b(adapter_t *adapter)
3216 if (!uses_xaui(adapter)) {
3217 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET |
3219 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALRESET, 0);
3220 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0,
3222 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_XGM_IMPSETUPDATE,
3224 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, F_CALUPDATE, 0);
3225 t3_set_reg_field(adapter, A_XGM_RGMII_IMP, 0, F_CALUPDATE);
3244 static int wrreg_wait(adapter_t *adapter, unsigned int addr, u32 val)
3246 t3_write_reg(adapter, addr, val);
3247 (void) t3_read_reg(adapter, addr); /* flush */
3248 if (!(t3_read_reg(adapter, addr) & F_BUSY))
3250 CH_ERR(adapter, "write to MC7 register 0x%x timed out\n", addr);
3269 adapter_t *adapter = mc7->adapter;
3275 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3280 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
3281 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3285 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
3286 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
3288 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
3290 CH_ERR(adapter, "%s MC7 calibration timed out\n",
3296 t3_write_reg(adapter, mc7->offset + A_MC7_PARM,
3302 t3_write_reg(adapter, mc7->offset + A_MC7_CFG,
3304 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3307 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL, F_DLLENB,
3312 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
3313 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE2, 0) ||
3314 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE3, 0) ||
3315 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
3319 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);
3320 t3_set_reg_field(adapter, mc7->offset + A_MC7_DLL,
3325 if (wrreg_wait(adapter, mc7->offset + A_MC7_PRE, 0) ||
3326 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
3327 wrreg_wait(adapter, mc7->offset + A_MC7_REF, 0) ||
3328 wrreg_wait(adapter, mc7->offset + A_MC7_MODE,
3330 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val | 0x380) ||
3331 wrreg_wait(adapter, mc7->offset + A_MC7_EXT_MODE1, val))
3338 t3_write_reg(adapter, mc7->offset + A_MC7_REF,
3340 (void) t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */
3342 t3_write_reg(adapter, mc7->offset + A_MC7_ECC,
3344 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);
3345 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
3346 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
3348 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
3349 (void) t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
3354 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
3357 CH_ERR(adapter, "%s MC7 BIST timed out\n", mc7->name);
3362 t3_set_reg_field(adapter, mc7->offset + A_MC7_CFG, 0, F_RDY);
3423 * @adapter: the adapter
3434 int t3_init_hw(adapter_t *adapter, u32 fw_params)
3437 const struct vpd_params *vpd = &adapter->params.vpd;
3439 if (adapter->params.rev > 0)
3440 calibrate_xgm_t3b(adapter);
3441 else if (calibrate_xgm(adapter))
3444 if (adapter->params.nports > 2)
3445 t3_mac_reset(&adap2pinfo(adapter, 0)->mac);
3448 partition_mem(adapter, &adapter->params.tp);
3450 if (mc7_init(&adapter->pmrx, vpd->mclk, vpd->mem_timing) ||
3451 mc7_init(&adapter->pmtx, vpd->mclk, vpd->mem_timing) ||
3452 mc7_init(&adapter->cm, vpd->mclk, vpd->mem_timing) ||
3453 t3_mc5_init(&adapter->mc5, adapter->params.mc5.nservers,
3454 adapter->params.mc5.nfilters,
3455 adapter->params.mc5.nroutes))
3459 if (tp_init(adapter, &adapter->params.tp))
3463 t3_tp_set_coalescing_size(adapter,
3464 uimin(adapter->params.sge.max_pkt_size,
3466 t3_tp_set_max_rxsize(adapter,
3467 uimin(adapter->params.sge.max_pkt_size, 16384U));
3468 ulp_config(adapter, &adapter->params.tp);
3470 if (is_pcie(adapter))
3471 config_pcie(adapter);
3473 t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_CLIDECEN);
3475 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
3476 t3_write_reg(adapter, A_PM1_RX_MODE, 0);
3477 t3_write_reg(adapter, A_PM1_TX_MODE, 0);
3478 chan_init_hw(adapter, adapter->params.chan_map);
3479 t3_sge_init(adapter, &adapter->params.sge);
3481 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3482 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3484 (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3488 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
3490 CH_ERR(adapter, "uP initialization timed out\n");
3501 * @adapter: the adapter
3507 static void __devinit get_pci_mode(adapter_t *adapter, struct pci_params *p)
3512 pcie_cap = t3_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
3518 t3_os_pci_read_config_2(adapter, pcie_cap + PCI_EXP_LNKSTA,
3524 pcie_mode = t3_read_reg(adapter, A_PCIX_MODE);
3582 static void __devinit mc7_prep(adapter_t *adapter, struct mc7 *mc7,
3587 mc7->adapter = adapter;
3590 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3595 void mac_prep(struct cmac *mac, adapter_t *adapter, int index)
3597 mac->adapter = adapter;
3598 mac->multiport = adapter->params.nports > 2;
3608 if (adapter->params.rev == 0 && uses_xaui(adapter)) {
3609 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset,
3610 is_10G(adapter) ? 0x2901c04 : 0x2301c04);
3611 t3_set_reg_field(adapter, A_XGM_PORT_CFG + mac->offset,
3618 * @adapter: the adapter
3619 * @ai: contains information about the adapter type and properties
3625 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai)
3627 u32 val = V_PORTSPEED(is_10G(adapter) || adapter->params.nports > 2 ?
3630 mi1_init(adapter, ai);
3631 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
3632 V_I2C_CLKDIV(adapter->params.vpd.cclk / 80 - 1));
3633 t3_write_reg(adapter, A_T3DBG_GPIO_EN,
3635 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
3637 if (adapter->params.rev == 0 || !uses_xaui(adapter))
3641 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3642 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
3645 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3646 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
3647 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val);
3648 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
3652 * t3_reset_adapter - reset the adapter
3653 * @adapter: the adapter
3655 * Reset the adapter.
3657 static int t3_reset_adapter(adapter_t *adapter)
3660 adapter->params.rev < T3_REV_B2 && is_pcie(adapter);
3664 t3_os_pci_save_state(adapter);
3665 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
3673 t3_os_pci_read_config_2(adapter, 0x00, &devid);
3682 t3_os_pci_restore_state(adapter);
3688 * @adapter: the adapter
3689 * @ai: contains information about the adapter type and properties
3691 * Initialize adapter SW state for the various HW modules, set initial
3692 * values for some adapter tunables, take PHYs out of reset, and
3695 int __devinit t3_prep_adapter(adapter_t *adapter,
3701 get_pci_mode(adapter, &adapter->params.pci);
3703 adapter->params.info = ai;
3704 adapter->params.nports = ai->nports0 + ai->nports1;
3705 adapter->params.chan_map = !!ai->nports0 | (!!ai->nports1 << 1);
3706 adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
3707 adapter->params.linkpoll_period = 0;
3708 if (adapter->params.nports > 2)
3709 adapter->params.stats_update_period = VSC_STATS_ACCUM_SECS;
3711 adapter->params.stats_update_period = is_10G(adapter) ?
3713 adapter->params.pci.vpd_cap_addr =
3714 t3_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
3716 ret = get_vpd_params(adapter, &adapter->params.vpd);
3720 if (reset && t3_reset_adapter(adapter))
3723 t3_sge_prep(adapter, &adapter->params.sge);
3725 if (adapter->params.vpd.mclk) {
3726 struct tp_params *p = &adapter->params.tp;
3728 mc7_prep(adapter, &adapter->pmrx, MC7_PMRX_BASE_ADDR, "PMRX");
3729 mc7_prep(adapter, &adapter->pmtx, MC7_PMTX_BASE_ADDR, "PMTX");
3730 mc7_prep(adapter, &adapter->cm, MC7_CM_BASE_ADDR, "CM");
3732 p->nchan = adapter->params.chan_map == 3 ? 2 : 1;
3733 p->pmrx_size = t3_mc7_size(&adapter->pmrx);
3734 p->pmtx_size = t3_mc7_size(&adapter->pmtx);
3735 p->cm_size = t3_mc7_size(&adapter->cm);
3739 p->tx_pg_size = is_10G(adapter) ? 64 * 1024 : 16 * 1024;
3743 adapter->params.rev > 0 ? 12 : 6;
3744 p->tre = fls(adapter->params.vpd.cclk / (1000 / TP_TMR_RES)) -
3746 p->dack_re = fls(adapter->params.vpd.cclk / 10) - 1; /* 100us */
3749 adapter->params.offload = t3_mc7_size(&adapter->pmrx) &&
3750 t3_mc7_size(&adapter->pmtx) &&
3751 t3_mc7_size(&adapter->cm);
3753 if (is_offload(adapter)) {
3754 adapter->params.mc5.nservers = DEFAULT_NSERVERS;
3755 adapter->params.mc5.nfilters = adapter->params.rev > 0 ?
3757 adapter->params.mc5.nroutes = 0;
3758 t3_mc5_prep(adapter, &adapter->mc5, MC5_MODE_144_BIT);
3761 init_mtus(adapter->params.mtus);
3762 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
3766 early_hw_init(adapter, ai);
3768 if (adapter->params.nports > 2 &&
3769 (ret = t3_vsc7323_init(adapter, adapter->params.nports)))
3772 for_each_port(adapter, i) {
3774 struct port_info *p = adap2pinfo(adapter, i);
3776 while (!adapter->params.vpd.port_type[j])
3779 p->port_type = &port_types[adapter->params.vpd.port_type[j]];
3780 p->port_type->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
3782 mac_prep(&p->mac, adapter, j);
3790 memcpy(hw_addr, adapter->params.vpd.eth_base, 5);
3791 hw_addr[5] = adapter->params.vpd.eth_base[5] + i;
3793 t3_os_set_hw_addr(adapter, i, hw_addr);
3797 adapter->params.linkpoll_period = 10;
3803 void t3_led_ready(adapter_t *adapter)
3805 t3_set_reg_field(adapter, A_T3DBG_GPIO_EN, F_GPIO0_OUT_VAL,
3809 void t3_port_failover(adapter_t *adapter, int port)
3814 t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE,
3818 void t3_failover_done(adapter_t *adapter, int port)
3820 t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE,
3824 void t3_failover_clear(adapter_t *adapter)
3826 t3_set_reg_field(adapter, A_MPS_CFG, F_PORT0ACTIVE | F_PORT1ACTIVE,
Indexes created Mon Oct 13 08:09:50 GMT 2025