Cross Reference: /src/sys/dev/pci/cxgb/cxgb_t3

Lines Matching defs:cause
1537     u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
1539     if (cause & F_CE) {
1549     if (cause & F_UE) {
1559     if (G_PE(cause)) {
1562              mc7->name, G_PE(cause));
1565     if (cause & F_AE) {
1576     if (cause & MC7_INTR_FATAL)
1579     t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
1589     u32 cause;
1594     cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset);
1596     if (cause & V_TXFIFO_PRTY_ERR(M_TXFIFO_PRTY_ERR)) {
1600     if (cause & V_RXFIFO_PRTY_ERR(M_RXFIFO_PRTY_ERR)) {
1604     if (cause & F_TXFIFO_UNDERRUN)
1606     if (cause & F_RXFIFO_OVERFLOW)
1608     if (cause & V_SERDES_LOS(M_SERDES_LOS))
1610     if (cause & F_XAUIPCSCTCERR)
1612     if (cause & F_XAUIPCSALIGNCHANGE)
1615     t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);
1616     if (cause & XGM_INTR_FATAL)
1618     return cause != 0;
1627     u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1638         if (cause & mask) {
1648     t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause);
1662     u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);
1664     cause &= adapter->slow_intr_mask;
1665     if (!cause)
1667     if (cause & F_PCIM0) {
1673     if (cause & F_SGE3)
1675     if (cause & F_MC7_PMRX)
1677     if (cause & F_MC7_PMTX)
1679     if (cause & F_MC7_CM)
1681     if (cause & F_CIM)
1683     if (cause & F_TP1)
1685     if (cause & F_ULP2_RX)
1687     if (cause & F_ULP2_TX)
1689     if (cause & F_PM1_RX)
1691     if (cause & F_PM1_TX)
1693     if (cause & F_CPL_SWITCH)
1695     if (cause & F_MPS0)
1697     if (cause & F_MC5A)
1699     if (cause & F_XGMAC0_0)
1701     if (cause & F_XGMAC0_1)
1703     if (cause & F_T3DBG)
1707     t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
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