Lines Matching refs:t3_read_reg
62 u32 val = t3_read_reg(adapter, reg);
108 u32 v = t3_read_reg(adapter, addr) & ~mask;
111 (void) t3_read_reg(adapter, addr); /* flush */
132 *vals++ = t3_read_reg(adap, data_reg);
171 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
173 val = t3_read_reg(adap,
178 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
180 val64 = t3_read_reg(adap,
228 *valp = t3_read_reg(adapter, A_MI1_DATA);
275 *valp = t3_read_reg(adapter, A_MI1_DATA);
718 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
723 *valp = t3_read_reg(adapter, A_SF_DATA);
743 if (t3_read_reg(adapter, A_SF_OP) & F_BUSY)
880 *vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
903 vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
1087 if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
1095 *valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA);
1232 unsigned int status = t3_read_reg(adapter, reg) & mask;
1350 if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR)
1352 t3_read_reg(adapter, A_PCIE_PEX_ERR));
1537 u32 cause = t3_read_reg(adapter, mc7->offset + A_MC7_INT_CAUSE);
1543 t3_read_reg(adapter, mc7->offset + A_MC7_CE_ADDR),
1544 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA0),
1545 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA1),
1546 t3_read_reg(adapter, mc7->offset + A_MC7_CE_DATA2));
1553 t3_read_reg(adapter, mc7->offset + A_MC7_UE_ADDR),
1554 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA0),
1555 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA1),
1556 t3_read_reg(adapter, mc7->offset + A_MC7_UE_DATA2));
1569 addr = t3_read_reg(adapter,
1594 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset);
1627 u32 i, cause = t3_read_reg(adapter, A_T3DBG_INT_CAUSE);
1662 u32 cause = t3_read_reg(adapter, A_PL_INT_CAUSE0);
1708 (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1762 (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1775 (void) t3_read_reg(adapter, A_PL_INT_ENABLE0); /* flush */
1817 (void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
1918 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1958 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
1999 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2036 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2063 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2087 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2111 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2135 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2168 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2188 return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0));
2206 if (t3_read_reg(adapter, A_SG_CONTEXT_CMD) & F_CONTEXT_CMD_BUSY)
2214 data[0] = t3_read_reg(adapter, A_SG_CONTEXT_DATA0);
2215 data[1] = t3_read_reg(adapter, A_SG_CONTEXT_DATA1);
2216 data[2] = t3_read_reg(adapter, A_SG_CONTEXT_DATA2);
2217 data[3] = t3_read_reg(adapter, A_SG_CONTEXT_DATA3);
2342 val = t3_read_reg(adapter, A_TP_RSS_LKP_TABLE);
2353 val = t3_read_reg(adapter, A_TP_RSS_MAP_TABLE);
2388 val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
2654 val = t3_read_reg(adap, A_TP_PARA_REG3);
2814 val = t3_read_reg(adap, A_TP_MTU_TABLE);
2836 incr[mtu][w] = (unsigned short)t3_read_reg(adap,
2867 pace_vals[i] = t3_read_reg(adap, A_TP_PACE_TABLE) * tick_ns;
2982 (void) t3_read_reg(adapter, A_TP_PIO_DATA);
3020 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3048 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3054 t3_read_reg(adap, A_TP_TM_PIO_DATA);
3075 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3090 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3194 (void) t3_read_reg(adapter, A_XGM_XAUI_IMP);
3196 v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
3247 (void) t3_read_reg(adapter, addr); /* flush */
3248 if (!(t3_read_reg(adapter, addr) & F_BUSY))
3275 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3281 val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3286 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
3288 if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
3304 (void) t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
3340 (void) t3_read_reg(adapter, mc7->offset + A_MC7_REF); /* flush */
3349 (void) t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP); /* flush */
3354 val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
3397 fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
3399 G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
3484 (void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
3488 } while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
3524 pcie_mode = t3_read_reg(adapter, A_PCIX_MODE);
3590 cfg = t3_read_reg(adapter, mc7->offset + A_MC7_CFG);
3642 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
3646 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
3648 (void) t3_read_reg(adapter, A_XGM_PORT_CFG);
3706 adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
Indexes created Fri Oct 17 09:09:57 GMT 2025