Lines Matching refs:t3_write_reg
91 t3_write_reg(adapter, p->reg_addr + offset, p->val);
110 t3_write_reg(adapter, addr, v | val);
131 t3_write_reg(adap, addr_reg, start_idx);
168 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR,
170 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
206 t3_write_reg(adap, A_MI1_CFG, val);
224 t3_write_reg(adapter, A_MI1_ADDR, addr);
225 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(2));
243 t3_write_reg(adapter, A_MI1_ADDR, addr);
244 t3_write_reg(adapter, A_MI1_DATA, val);
245 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
266 t3_write_reg(adapter, A_MI1_ADDR, addr);
267 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
268 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
271 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(3));
288 t3_write_reg(adapter, A_MI1_ADDR, addr);
289 t3_write_reg(adapter, A_MI1_DATA, reg_addr);
290 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(0));
293 t3_write_reg(adapter, A_MI1_DATA, val);
294 t3_write_reg(adapter, A_MI1_OP, V_MDI_OP(1));
720 t3_write_reg(adapter, A_SF_OP, V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
745 t3_write_reg(adapter, A_SF_DATA, val);
746 t3_write_reg(adapter, A_SF_OP,
874 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
897 t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
1091 t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr);
1123 t3_write_reg(adapter, A_XGM_XAUI_ACT_CTRL + mac->offset,
1247 t3_write_reg(adapter, reg, status);
1579 t3_write_reg(adapter, mc7->offset + A_MC7_INT_CAUSE, cause);
1615 t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);
1648 t3_write_reg(adapter, A_T3DBG_INT_CAUSE, cause);
1707 t3_write_reg(adapter, A_PL_INT_CAUSE0, cause);
1743 t3_write_reg(adapter, A_CPL_INTR_ENABLE,
1745 t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
1749 t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
1750 t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
1753 t3_write_reg(adapter, A_T3DBG_GPIO_ACT_LOW,
1755 t3_write_reg(adapter, A_T3DBG_INT_ENABLE,
1758 t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
1760 t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
1761 t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
1774 t3_write_reg(adapter, A_PL_INT_ENABLE0, 0);
1812 t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff);
1815 t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff);
1816 t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff);
1832 t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, XGM_INTR_MASK);
1848 t3_write_reg(adapter, A_XGM_INT_ENABLE + pi->mac.offset, 0);
1864 t3_write_reg(adapter, A_XGM_INT_CAUSE + pi->mac.offset, 0xffffffff);
1882 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0xffffffff);
1883 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0xffffffff);
1884 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0xffffffff);
1885 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0xffffffff);
1886 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
1922 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_EC_INDEX(cidx) |
1924 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, V_EC_SIZE(size) |
1927 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, (u32)base_addr);
1929 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
1962 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, (u32)base_addr);
1964 t3_write_reg(adapter, A_SG_CONTEXT_DATA1,
1967 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, V_FL_SIZE(size) |
1970 t3_write_reg(adapter, A_SG_CONTEXT_DATA3,
2003 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size) |
2005 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr);
2009 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2011 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, fl_thres);
2040 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, V_CQ_SIZE(size));
2041 t3_write_reg(adapter, A_SG_CONTEXT_DATA1, (u32)base_addr);
2043 t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
2047 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
2066 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2067 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2068 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2069 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, F_EC_VALID);
2070 t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_EC_VALID(enable));
2071 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2090 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, 0);
2091 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2092 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, V_FL_SIZE(M_FL_SIZE));
2093 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2094 t3_write_reg(adapter, A_SG_CONTEXT_DATA2, 0);
2095 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2114 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2115 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2116 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2117 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2118 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2119 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2138 t3_write_reg(adapter, A_SG_CONTEXT_MASK0, V_CQ_SIZE(M_CQ_SIZE));
2139 t3_write_reg(adapter, A_SG_CONTEXT_MASK1, 0);
2140 t3_write_reg(adapter, A_SG_CONTEXT_MASK2, 0);
2141 t3_write_reg(adapter, A_SG_CONTEXT_MASK3, 0);
2142 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, 0);
2143 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2171 t3_write_reg(adapter, A_SG_CONTEXT_DATA0, credits << 16);
2172 t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) |
2182 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2209 t3_write_reg(adapter, A_SG_CONTEXT_CMD,
2311 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE, val);
2316 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2322 t3_write_reg(adapter, A_TP_RSS_CONFIG, rss_config);
2340 t3_write_reg(adapter, A_TP_RSS_LKP_TABLE,
2351 t3_write_reg(adapter, A_TP_RSS_MAP_TABLE,
2387 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2389 t3_write_reg(adap, A_TP_PIO_DATA, val);
2424 t3_write_reg((adap), A_ ## reg, (start)); \
2485 t3_write_reg(adap, A_TP_PMM_SIZE,
2488 t3_write_reg(adap, A_TP_PMM_TX_BASE, 0);
2489 t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size);
2490 t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs);
2494 t3_write_reg(adap, A_TP_PMM_RX_BASE, 0);
2495 t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size);
2496 t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs);
2502 t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs);
2507 t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m);
2515 t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m);
2516 t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m);
2527 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2528 t3_write_reg(adap, A_TP_PIO_DATA, val);
2533 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2536 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2539 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2545 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2546 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
2555 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
2556 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
2569 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2570 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2571 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2572 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2608 t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) |
2611 t3_write_reg(adap, A_TP_DACK_TIMER,
2613 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100);
2614 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504);
2615 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908);
2616 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c);
2617 t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) |
2624 t3_write_reg(adap, A_TP_MSL,
2626 t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN));
2627 t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS);
2628 t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS);
2629 t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS);
2630 t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS);
2631 t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS);
2632 t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS);
2633 t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS);
2662 t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |
2665 t3_write_reg(adap, A_TP_PARA_REG3, val);
2679 t3_write_reg(adap, A_TP_PARA_REG7,
2784 t3_write_reg(adap, A_TP_MTU_TABLE,
2793 t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
2813 t3_write_reg(adap, A_TP_MTU_TABLE, 0xff000000 | i);
2834 t3_write_reg(adap, A_TP_CCTRL_TABLE,
2866 t3_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
2886 t3_write_reg(adap, A_TP_PACE_TABLE, (start << 16) |
2891 t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \
2892 t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \
2897 t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \
2898 t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \
2912 t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff);
2929 t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++));
2930 t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, cpu_to_be32(*buf++));
2931 t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++));
2932 t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++));
2933 t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++));
2935 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
3018 t3_write_reg(adap, A_TP_TM_PIO_ADDR,
3025 t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
3047 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3053 t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
3074 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3089 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3114 t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE);
3122 t3_write_reg(adap, A_TP_RESET, F_TPRESET);
3157 t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_ENFORCEPKT |
3160 t3_write_reg(adap, A_PM1_TX_CFG,
3163 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
3165 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xd9c8);
3166 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfbea);
3170 t3_write_reg(adap, A_ULPTX_DMA_WEIGHT,
3172 t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN |
3175 t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000);
3177 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
3180 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE,
3182 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xba98);
3183 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfedc);
3193 t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
3198 t3_write_reg(adapter, A_XGM_XAUI_IMP,
3206 t3_write_reg(adapter, A_XGM_RGMII_IMP,
3217 t3_write_reg(adapter, A_XGM_RGMII_IMP, F_CALRESET |
3246 t3_write_reg(adapter, addr, val);
3280 t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
3285 t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
3296 t3_write_reg(adapter, mc7->offset + A_MC7_PARM,
3302 t3_write_reg(adapter, mc7->offset + A_MC7_CFG,
3319 t3_write_reg(adapter, mc7->offset + A_MC7_MODE, 0x100);
3338 t3_write_reg(adapter, mc7->offset + A_MC7_REF,
3342 t3_write_reg(adapter, mc7->offset + A_MC7_ECC,
3344 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_DATA, 0);
3345 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_BEG, 0);
3346 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_ADDR_END,
3348 t3_write_reg(adapter, mc7->offset + A_MC7_BIST_OP, V_OP(1));
3417 t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
3475 t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
3476 t3_write_reg(adapter, A_PM1_RX_MODE, 0);
3477 t3_write_reg(adapter, A_PM1_TX_MODE, 0);
3481 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params);
3482 t3_write_reg(adapter, A_CIM_BOOT_CFG,
3609 t3_write_reg(adapter, A_XGM_SERDES_CTRL + mac->offset,
3631 t3_write_reg(adapter, A_I2C_CFG, /* set for 80KHz */
3633 t3_write_reg(adapter, A_T3DBG_GPIO_EN,
3635 t3_write_reg(adapter, A_MC5_DB_SERVER_INDEX, 0);
3641 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3645 t3_write_reg(adapter, A_XGM_PORT_CFG, val);
3647 t3_write_reg(adapter, XGM_REG(A_XGM_PORT_CFG, 1), val);
3665 t3_write_reg(adapter, A_PL_RST, F_CRSTWRM | F_CRSTWRMMODE);
Indexes created Sat Oct 18 23:09:54 GMT 2025