Lines Matching defs:adap
62 adapter_t *adap = mac->adapter;
65 t3_write_reg(adap, ctrl, adap->params.vpd.xauicfg[macidx(mac)] |
69 (void)t3_read_reg(adap, ctrl);
73 t3_set_reg_field(adap, ctrl, clear[i], 0);
107 adapter_t *adap = mac->adapter;
110 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
111 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
113 t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft);
114 t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
116 uses_xaui(adap) ? 0 : F_RXSTRFRWRD);
118 if (uses_xaui(adap)) {
119 if (adap->params.rev == 0) {
120 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
122 if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft,
124 CH_ERR(adap,
129 t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
137 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
139 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0,
141 t3_set_reg_field(adap, A_XGM_RX_CFG + oft, 0, F_COPYPREAMBLE |
143 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft,
146 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
147 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
151 if (is_10G(adap) || mac->multiport)
153 else if (uses_xaui(adap))
157 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
158 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
159 if ((val & F_PCS_RESET_) && adap->params.rev) {
171 adapter_t *adap = mac->adapter;
177 t3_set_reg_field(adap, A_MPS_CFG, F_PORT0ACTIVE, 0);
179 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE, 0);
182 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
183 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
188 if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
190 CH_ERR(adap, "MAC %d Rx fifo drain failed\n",
195 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0); /*MAC in reset*/
196 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
199 if (is_10G(adap))
201 else if (uses_xaui(adap))
205 t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
206 (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
207 if ((val & F_PCS_RESET_) && adap->params.rev) {
211 t3_write_reg(adap, A_XGM_RX_CFG + oft,
217 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT0ACTIVE);
219 t3_set_reg_field(adap, A_MPS_CFG, 0, F_PORT1ACTIVE);
304 adapter_t *adap = mac->adapter;
311 t3_set_reg_field(adap, A_XGM_RX_CFG + oft, F_COPYALLFRAMES,
334 t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
335 t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
351 adapter_t *adap = mac->adapter;
363 return t3_vsc7323_set_mtu(adap, mtu - 4, mac->ext_port);
365 if (adap->params.rev == T3_REV_B2 &&
366 (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
368 v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
369 t3_set_reg_field(adap, A_XGM_RX_CFG + mac->offset,
373 if (t3_wait_op_done(adap,
376 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
380 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
381 t3_write_reg(adap, A_XGM_RX_CFG + mac->offset, v);
384 t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + mac->offset, mtu);
392 v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
399 t3_write_reg(adap, A_XGM_RXFIFO_CFG + mac->offset, v);
402 thres = (adap->params.vpd.cclk * 1000) / 15625;
404 if (is_10G(adap))
408 t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + mac->offset,
414 if (adap->params.rev > 0)
415 t3_write_reg(adap, A_XGM_PAUSE_TIMER + mac->offset,
417 t3_write_reg(adap, A_XGM_TX_PAUSE_QUANTA + mac->offset,
425 adapter_t *adap = mac->adapter;
431 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
433 val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(t3_read_reg(adap,
435 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
437 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
439 return t3_vsc7323_set_speed_fc(adap, speed, fc, mac->ext_port);
453 t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
457 val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
460 val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(t3_read_reg(adap,
462 t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
464 t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
472 adapter_t *adap = mac->adapter;
477 return t3_vsc7323_enable(adap, mac->ext_port, which);
480 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
481 t3_write_reg(adap, A_TP_PIO_DATA, 0xc0ede401);
482 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
483 t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
485 t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
487 t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
489 mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
491 mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
496 mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
504 t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
510 adapter_t *adap = mac->adapter;
513 return t3_vsc7323_disable(adap, mac->ext_port, which);
516 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
525 t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
526 if (is_10G(adap))
528 else if (uses_xaui(adap))
541 adapter_t *adap = mac->adapter;
548 tx_mcnt = t3_read_reg(adap, A_XGM_STAT_TX_FRAME_LOW);
549 rx_mcnt = t3_read_reg(adap, A_XGM_STAT_RX_FRAMES_LOW);
559 tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
563 t3_write_reg(adap, A_TP_PIO_ADDR,
565 tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
590 rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
612 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
613 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
614 t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, mac->txen);
615 t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
Indexes created Thu Oct 02 14:10:14 GMT 2025