Cross Reference: /src/sys/dev/pci/cxgb/cxgb

Lines Matching defs:oft
108     unsigned int oft = mac->offset;
110     t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
111     (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
113     t3_write_regs(adap, mac_reset_avp, ARRAY_SIZE(mac_reset_avp), oft);
114     t3_set_reg_field(adap, A_XGM_RXFIFO_CFG + oft,
120             t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
122             if (t3_wait_op_done(adap, A_XGM_SERDES_STATUS1 + oft,
129             t3_set_reg_field(adap, A_XGM_SERDES_CTRL + oft, 0,
137         t3_write_reg(adap, A_XGM_RX_MAX_PKT_SIZE + oft,
139         t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft, 0,
141         t3_set_reg_field(adap, A_XGM_RX_CFG + oft, 0, F_COPYPREAMBLE |
143         t3_set_reg_field(adap, A_XGM_TXFIFO_CFG + oft,
146         t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
147         t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
157     t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
158     (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);  /* flush */
172     unsigned int oft = mac->offset;
182     t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
183     (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
188     if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
195     t3_write_reg(adap, A_XGM_RESET_CTRL + oft, 0); /*MAC in reset*/
196     (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
205     t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
206     (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);  /* flush */
211     t3_write_reg(adap, A_XGM_RX_CFG + oft,
230     unsigned int oft = mac->offset + idx * 8;
235     t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1 + oft, addr_lo);
236     t3_write_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_HIGH_1 + oft, addr_hi);
305     unsigned int oft = mac->offset;
311     t3_set_reg_field(adap, A_XGM_RX_CFG + oft, F_COPYALLFRAMES,
334     t3_write_reg(adap, A_XGM_RX_HASH_LOW + oft, hash_lo);
335     t3_write_reg(adap, A_XGM_RX_HASH_HIGH + oft, hash_hi);
426     unsigned int oft = mac->offset;
431         val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
434                     A_XGM_RX_MAX_PKT_SIZE + oft)) / 8);
435         t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
437         t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
453         t3_set_reg_field(adap, A_XGM_PORT_CFG + oft,
457     val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
461                     A_XGM_RX_MAX_PKT_SIZE + oft)) / 8);
462     t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
464     t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
473     unsigned int oft = mac->offset;
485         t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
493                         oft)));
498                         oft)));
504         t3_write_reg(adap, A_XGM_RX_CTRL + oft, F_RXEN);
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