Cross Reference: /src/sys/dev/pci/cxgb/cxgb

Lines Matching refs:t3_read_reg
69     (void)t3_read_reg(adap, ctrl);
111     (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
158     (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);  /* flush */
183     (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
196     (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);    /* flush */
206     (void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft);  /* flush */
270         u32 v = t3_read_reg(mac->adapter, reg);
273     t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */
281         u32 v = t3_read_reg(mac->adapter, reg);
284     t3_read_reg(mac->adapter, A_XGM_RX_EXACT_MATCH_LOW_1); /* flush */
366         (t3_read_reg(adap, A_XGM_RX_CTRL + mac->offset) & F_RXEN)) {
368         v = t3_read_reg(adap, A_XGM_RX_CFG + mac->offset);
392     v = t3_read_reg(adap, A_XGM_RXFIFO_CFG + mac->offset);
431         val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
433         val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(t3_read_reg(adap,
457     val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
460         val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(t3_read_reg(adap,
489         mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
491         mac->tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
496         mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
548       tx_mcnt = t3_read_reg(adap, A_XGM_STAT_TX_FRAME_LOW);
549       rx_mcnt = t3_read_reg(adap, A_XGM_STAT_RX_FRAMES_LOW);
559         tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
565             tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
590         rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
613         t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);  /* flush */
615         t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset);  /* flush */
633 #define RMON_READ(mac, addr) t3_read_reg(mac->adapter, addr + mac->offset)
688     v = t3_read_reg(mac->adapter, A_TP_MIB_RDATA);
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