Cross Reference: /src/sys/dev/pci/emuxki.c

Lines Matching defs:emuxki_write
98 static void	emuxki_write(struct emuxki_softc *, int, int, uint32_t);
342 emuxki_write(struct emuxki_softc *sc, int ch, int addr, uint32_t data)
500 	emuxki_write(sc, 0, EMU_CLIEL, 0);
501 	emuxki_write(sc, 0, EMU_CLIEH, 0);
502 	emuxki_write(sc, 0, EMU_SOLEL, 0);
503 	emuxki_write(sc, 0, EMU_SOLEH, 0);
506 	emuxki_write(sc, 0, X1(DBG), X1(DBG_SINGLE_STEP));
539 	emuxki_write(sc, 0, EMU_CLIEL, 0);
540 	emuxki_write(sc, 0, EMU_CLIEH, 0);
541 	emuxki_write(sc, 0, EMU_SOLEL, 0);
542 	emuxki_write(sc, 0, EMU_SOLEH, 0);
545 	emuxki_write(sc, 0, EMU_MICBS, EMU_RECBS_BUFSIZE_NONE);
546 	emuxki_write(sc, 0, EMU_MICBA, 0);
547 	emuxki_write(sc, 0, EMU_FXBS, EMU_RECBS_BUFSIZE_NONE);
548 	emuxki_write(sc, 0, EMU_FXBA, 0);
549 	emuxki_write(sc, 0, EMU_ADCBS, EMU_RECBS_BUFSIZE_NONE);
550 	emuxki_write(sc, 0, EMU_ADCBA, 0);
553 		emuxki_write
554 		emuxki_write(sc, 0, EMU_AC97SLOT,
560 		emuxki_write(sc, i, EMU_CHAN_DCYSUSV, 0x7f7f);
561 		emuxki_write(sc, i, EMU_CHAN_IP, EMU_CHAN_IP_UNITY);
562 		emuxki_write(sc, i, EMU_CHAN_VTFT, 0xffff);
563 		emuxki_write(sc, i, EMU_CHAN_CVCF, 0xffff);
564 		emuxki_write(sc, i, EMU_CHAN_PTRX, 0);
565 		emuxki_write(sc, i, EMU_CHAN_CPF, 0);
566 		emuxki_write(sc, i, EMU_CHAN_CCR, 0);
567 		emuxki_write(sc, i, EMU_CHAN_PSST, 0);
568 		emuxki_write(sc, i, EMU_CHAN_DSL, 0);
569 		emuxki_write(sc, i, EMU_CHAN_CCCA, EMU_CHAN_CCCA_INTERPROM_1);
570 		emuxki_write(sc, i, EMU_CHAN_Z1, 0);
571 		emuxki_write(sc, i, EMU_CHAN_Z2, 0);
572 		emuxki_write(sc, i, EMU_CHAN_MAPA, 0xffffffff);
573 		emuxki_write(sc, i, EMU_CHAN_MAPB, 0xffffffff);
574 		emuxki_write(sc, i, EMU_CHAN_FXRT, 0x32100000);
575 		emuxki_write(sc, i, EMU_CHAN_ATKHLDM, 0);
576 		emuxki_write(sc, i, EMU_CHAN_DCYSUSM, 0);
577 		emuxki_write(sc, i, EMU_CHAN_IFATN, 0xffff);
578 		emuxki_write(sc, i, EMU_CHAN_PEFE, 0x007f);
579 		emuxki_write(sc, i, EMU_CHAN_FMMOD, 0);
580 		emuxki_write(sc, i, EMU_CHAN_TREMFRQ, 0);
581 		emuxki_write(sc, i, EMU_CHAN_FM2FRQ2, 0);
582 		emuxki_write(sc, i, EMU_CHAN_TEMPENV, 0);
585 		emuxki_write(sc, i, EMU_CHAN_LFOVAL2, 0x8000);
586 		emuxki_write(sc, i, EMU_CHAN_LFOVAL1, 0x8000);
587 		emuxki_write(sc, i, EMU_CHAN_ATKHLDV, 0x7f7f);
588 		emuxki_write(sc, i, EMU_CHAN_ENVVOL, 0);
589 		emuxki_write(sc, i, EMU_CHAN_ENVVAL, 0x8000);
602 	emuxki_write(sc, 0, EMU_SPCS0, spcs);
603 	emuxki_write(sc, 0, EMU_SPCS1, spcs);
604 	emuxki_write(sc, 0, EMU_SPCS2, spcs);
608 		emuxki_write(sc, 0, EMU_A2_SPDIF_SAMPLERATE,
627 		emuxki_write(sc, 0, EMU_A2_SPDIF_SAMPLERATE,
643 	emuxki_write(sc, 0, EMU_PTB, DMAADDR(sc->ptb));
645 	emuxki_write(sc, 0, EMU_TCBS, 0);	/* This means 16K TCB */
646 	emuxki_write(sc, 0, EMU_TCB, 0);	/* No TCB use for now */
712 	emuxki_write(sc, 0, reg, loword);
713 	emuxki_write(sc, 0, reg + 1, hiword);
725 		emuxki_write(sc, 0, EMU_DSP_GPR(pc), 0);
727 		emuxki_write(sc, 0, EMU_TANKMEMDATAREGBASE + pc, 0);
728 		emuxki_write(sc, 0, EMU_TANKMEMADDRREGBASE + pc, 0);
732 	emuxki_write(sc, 0, X1(DBG), X1(DBG_SINGLE_STEP));
786 	emuxki_write(sc, 0, X1(DBG), 0);
803 	emuxki_write(sc, ch, EMU_CHAN_DSL,
807 	emuxki_write(sc, ch, EMU_CHAN_PSST,
811 	emuxki_write(sc, ch, EMU_CHAN_VTFT,
815 	emuxki_write(sc, ch, EMU_CHAN_CVCF,
819 	emuxki_write(sc, ch, EMU_CHAN_PTRX,
825 	emuxki_write(sc, ch, EMU_CHAN_CPF,
835 	emuxki_write(sc, ch, EMU_CHAN_CPF, EMU_CHAN_CPF_STOP_MASK);
837 	emuxki_write(sc, ch, EMU_CHAN_CVCF, 0);
910 	emuxki_write(sc, 0, EMU_ADCCR, 0);
1222 	emuxki_write(sc, 0, EMU_ADCCR, 0);
1223 	emuxki_write(sc, 0, EMU_ADCBA, 0);
1224 	emuxki_write(sc, 0, EMU_ADCBS, 0);
1235 	emuxki_write(sc, 0, EMU_ADCCR,
1239 	emuxki_write(sc, 0, X1(ADCIDX), 0);
1240 	emuxki_write(sc, 0, EMU_ADCBA, DMAADDR(sc->rmem));
1243 	emuxki_write(sc, 0, EMU_ADCBS, EMU_REC_BUFSIZE_RECBS);
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