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Lines Matching refs:CSR_READ_4

214 	sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
222 		    CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
223 		    CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
362 		v = CSR_READ_4(sc, AGE_MDIO);
396 		v = CSR_READ_4(sc, AGE_MDIO);
444 		reg = CSR_READ_4(sc, AGE_MAC_CFG);
446 		CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
496 	status = CSR_READ_4(sc, AGE_INTR_STATUS);
567 	reg = CSR_READ_4(sc, AGE_SPI_CTRL);
580 		CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
584 			reg = CSR_READ_4(sc, AGE_TWSI_CTRL);
597 	ea[0] = CSR_READ_4(sc, AGE_PAR0);
598 	ea[1] = CSR_READ_4(sc, AGE_PAR1);
1172 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
1612 	CSR_READ_4(sc, AGE_MASTER_CFG);
1615 		if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
1626 	CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
1729 	reg = CSR_READ_4(sc, AGE_MASTER_CFG);
1771 		CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
1791 		reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
1798 		reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
1883 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
1943 	    CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
1947 	    CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
1949 	    CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
1951 		if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2092 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
2098 	reg = CSR_READ_4(sc, AGE_DMA_CFG);
2104 		if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2119 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
2125 	reg = CSR_READ_4(sc, AGE_DMA_CFG);
2131 		if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2278 	reg = CSR_READ_4(sc, AGE_MAC_CFG);
2296 	rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);