Lines Matching refs:CSR_WRITE_4
358 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
390 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
446 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
449 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
505 CSR_WRITE_4(sc, AGE_INTR_STATUS, status);
514 CSR_WRITE_4(sc, AGE_INTR_STATUS, status);
571 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
580 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) |
615 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
617 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
1195 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1611 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
1625 CSR_WRITE_4(sc, 0x12FC, 0x6500);
1626 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
1664 CSR_WRITE_4(sc, AGE_PAR0,
1666 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
1670 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
1672 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
1674 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
1676 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
1678 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
1680 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
1683 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
1689 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
1693 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
1709 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
1716 CSR_WRITE_4(sc, AGE_HDPX_CFG,
1735 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
1748 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
1752 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
1766 CSR_WRITE_4(sc, 0x12FC, 0x6500);
1771 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
1807 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
1812 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
1819 CSR_WRITE_4(sc, AGE_RXQ_CFG,
1829 CSR_WRITE_4(sc, AGE_TXQ_CFG,
1839 CSR_WRITE_4(sc, AGE_DMA_CFG,
1845 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
1852 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
1857 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
1858 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
1864 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1873 CSR_WRITE_4(sc, AGE_MAC_CFG,
1887 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
1888 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
1891 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
1931 CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
1932 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
1935 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
1942 CSR_WRITE_4(sc, AGE_DMA_CFG,
1946 CSR_WRITE_4(sc, AGE_TXQ_CFG,
1948 CSR_WRITE_4(sc, AGE_RXQ_CFG,
2095 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2101 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2122 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2128 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2282 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2336 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
2337 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
2338 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
Indexes created Sat Oct 18 08:10:09 GMT 2025