Lines Matching defs:pmcfg
789 uint32_t pmcfg;
793 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
794 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 |
797 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB |
799 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1063 uint32_t pmcfg;
1066 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1073 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1;
1074 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK);
1075 pmcfg |= PM_CFG_MAC_ASPM_CHK;
1076 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT);
1077 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB);
1087 pmcfg
1089 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT <<
1091 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
1092 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT <<
1094 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV;
1099 pmcfg |= PM_CFG_ASPM_L0S_ENB;
1101 pmcfg |= PM_CFG_ASPM_L1_ENB;
1105 pmcfg &= ~PM_CFG_ASPM_L0S_ENB;
1106 pmcfg &= ~(PM_CFG_SERDES_L1_ENB |
1109 pmcfg |= PM_CFG_CLK_SWH_L1;
1111 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK;
1114 pmcfg |= (7 <<
1119 pmcfg |= (4 <<
1123 pmcfg |= (15 <<
1129 pmcfg |= PM_CFG_SERDES_L1_ENB |
1132 pmcfg &= ~(PM_CFG_CLK_SWH_L1 |
1136 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB |
1138 pmcfg |= PM_CFG_CLK_SWH_L1;
1140 pmcfg |= PM_CFG_ASPM_L1_ENB;
1142 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1148 uint32_t pmcfg;
1150 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1151 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK;
1152 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT;
1153 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK;
1154 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT;
1155 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK;
1156 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT;
1157 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV;
1158 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S |
1165 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB;
1168 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
1172 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB |
1175 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK;
1177 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
2709 uint32_t pmcfg, reg;
2712 pmcfg = 0;
2719 pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
2720 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
2722 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB |
2724 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
2767 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB))
2769 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
Indexes created Thu Oct 02 01:09:59 GMT 2025