Cross Reference: /src/sys/dev/pci/if

Lines Matching refs:CSR_READ_4
222 		v = CSR_READ_4(sc, ALC_MDIO);
254 		v = CSR_READ_4(sc, ALC_MDIO);
294 		v = CSR_READ_4(sc, ALC_MDIO);
323 		v = CSR_READ_4(sc, ALC_MDIO);
371 		reg = CSR_READ_4(sc, ALC_MAC_CFG);
425 		v = CSR_READ_4(sc, ALC_MDIO);
457 		v = CSR_READ_4(sc, ALC_MDIO);
619 	opt = CSR_READ_4(sc, ALC_OPT_CFG);
620 	if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 &&
621 	    (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) {
633 				CSR_READ_4(sc, ALC_OPT_CFG);
658 		    CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
660 		CSR_READ_4(sc, ALC_WOL_CFG);
662 		CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
666 			if ((CSR_READ_4(sc, ALC_TWSI_CFG) &
684 				CSR_READ_4(sc, ALC_OPT_CFG);
721 		reg = CSR_READ_4(sc, ALC_SLD);
730 			reg = CSR_READ_4(sc, ALC_SLD);
743 		reg = CSR_READ_4(sc, ALC_EEPROM_LD);
747 				reg = CSR_READ_4(sc, ALC_EEPROM_LD);
758 					reg = CSR_READ_4(sc, ALC_EEPROM_LD);
776 	ea[0] = CSR_READ_4(sc, ALC_PAR0);
777 	ea[1] = CSR_READ_4(sc, ALC_PAR1);
793 		pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
933 	val = CSR_READ_4(sc, ALC_GPHY_CFG);
965 	val = CSR_READ_4(sc, ALC_LPI_CTL);
1014 		gphy = CSR_READ_4(sc, ALC_GPHY_CFG);
1066 	pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1150 	pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
1188 	val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV);
1194 		    CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB);
1196 		    CSR_READ_4(sc, ALC_PCIE_PHYMISC) |
1200 			val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2);
1234 		val = CSR_READ_4(sc, ALC_PDLL_TRNS1);
1237 		val = CSR_READ_4(sc, ALC_MASTER_CFG);
1425 	sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >>
1433 		    CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8,
1434 		    CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8);
2143 	reg = CSR_READ_4(sc, ALC_MAC_CFG);
2190 			CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2196 			CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2224 			*reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i);
2230 			*reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i);
2326 	status = CSR_READ_4(sc, ALC_INTR_STATUS);
2387 		prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX);
2673 	reg = CSR_READ_4(sc, ALC_MISC3);
2678 	reg = CSR_READ_4(sc, ALC_MISC);
2689 		reg = CSR_READ_4(sc, ALC_MISC2);
2719 			pmcfg = CSR_READ_4(sc, ALC_PM_CFG);
2728 	reg = CSR_READ_4(sc, ALC_MASTER_CFG);
2735 			if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0)
2743 		if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0)
2750 		reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
2763 			reg = CSR_READ_4(sc, ALC_MASTER_CFG);
2773 		reg = CSR_READ_4(sc, ALC_MISC3);
2777 		reg = CSR_READ_4(sc, ALC_MISC);
2788 		    CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN |
2851 	CSR_READ_4(sc, ALC_WOL_CFG);
2933 	reg = CSR_READ_4(sc, ALC_MASTER_CFG);
3058 		reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
3074 		reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN);
3216 	reg = CSR_READ_4(sc, ALC_DMA_CFG);
3267 	reg = CSR_READ_4(sc, ALC_MAC_CFG);
3273 		reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3296 	cfg = CSR_READ_4(sc, ALC_RXQ_CFG);
3304 	cfg = CSR_READ_4(sc, ALC_TXQ_CFG);
3316 	reg = CSR_READ_4(sc, ALC_RXQ_CFG);
3329 	reg = CSR_READ_4(sc, ALC_TXQ_CFG);
3336 		reg = CSR_READ_4(sc, ALC_IDLE_STATUS);
3443 	reg = CSR_READ_4(sc, ALC_MAC_CFG);
3462 	rxcfg = CSR_READ_4(sc, ALC_MAC_CFG);
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