Lines Matching refs:CSR_WRITE_4
218 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
250 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
289 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
318 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
373 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
415 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
421 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
446 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) |
452 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
632 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
657 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
659 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
662 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) |
683 CSR_WRITE_4(sc, ALC_OPT_CFG, opt);
727 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START);
754 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg |
799 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
944 CSR_WRITE_4(sc, ALC_GPHY_CFG, val);
946 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET);
967 CSR_WRITE_4(sc, ALC_LPI_CTL, val);
1020 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy);
1142 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1177 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
1190 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val);
1193 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG,
1195 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC,
1205 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val);
1236 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val);
1243 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
1250 CSR_WRITE_4(sc, ALC_MASTER_CFG, val);
2064 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX,
2167 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
2331 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT);
2364 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF);
2533 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX,
2676 CSR_WRITE_4(sc, ALC_MISC3, reg);
2687 CSR_WRITE_4(sc, ALC_MISC, reg);
2688 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
2691 CSR_WRITE_4(sc, ALC_MISC2, reg);
2692 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START);
2699 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN);
2700 CSR_WRITE_4(sc, ALC_MISC, reg);
2715 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1);
2724 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
2730 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2765 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2769 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg);
2776 CSR_WRITE_4(sc, ALC_MISC3, reg);
2781 CSR_WRITE_4(sc, ALC_MISC, reg);
2787 CSR_WRITE_4(sc, ALC_SERDES_LOCK,
2832 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB |
2837 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER,
2840 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0);
2844 CSR_WRITE_4(sc, ALC_PAR0, (uint32_t)eaddr[2] << 24
2846 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]);
2852 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
2855 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2856 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2858 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0);
2860 CSR_WRITE_4(sc, ALC_TD_RING_CNT,
2864 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2865 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2868 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0);
2869 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0);
2870 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0);
2873 CSR_WRITE_4(sc, ALC_RD_RING_CNT,
2887 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size);
2891 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr));
2894 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0);
2895 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0);
2896 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0);
2899 CSR_WRITE_4(sc, ALC_RRD_RING_CNT,
2902 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
2904 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr));
2905 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr));
2909 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0);
2910 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100);
2911 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000);
2912 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0);
2913 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0);
2914 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0);
2915 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000);
2916 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000);
2920 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD);
2928 CSR_WRITE_4(sc, ALC_IM_TIMER, reg);
2941 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg);
2946 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0));
2949 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3);
2950 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER,
2954 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4);
2955 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000));
2957 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0));
2965 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0));
2983 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen);
2987 CSR_WRITE_4(sc, ALC_HDS_CFG, 0);
2990 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG,
3000 CSR_WRITE_4(sc, ALC_HDPX_CFG,
3020 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg);
3030 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE);
3036 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg);
3042 CSR_WRITE_4(sc, ALC_WRR, reg);
3045 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH,
3066 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
3077 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH,
3086 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0);
3087 CSR_WRITE_4(sc, ALC_RSS_CPU, 0);
3105 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3137 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3164 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3171 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS);
3172 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3173 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0);
3212 CSR_WRITE_4(sc, ALC_INTR_MASK, 0);
3213 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3219 CSR_WRITE_4(sc, ALC_DMA_CFG, reg);
3226 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF);
3270 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3302 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg);
3306 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg);
3320 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3325 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg);
3332 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg);
3394 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons);
3448 CSR_WRITE_4(sc, ALC_MAC_CFG, reg);
3502 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]);
3503 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]);
3504 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg);
Indexes created Mon Oct 20 15:10:11 GMT 2025