Cross Reference: /src/sys/dev/pci/if

Lines Matching refs:CSR_READ_4
155 		v = CSR_READ_4(sc, ALE_MDIO);
196 		v = CSR_READ_4(sc, ALE_MDIO);
246 		reg = CSR_READ_4(sc, ALE_MAC_CFG);
296 	reg = CSR_READ_4(sc, ALE_SPI_CTRL);
308 		CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
312 			reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
325 	ea[0] = CSR_READ_4(sc, ALE_PAR0);
326 	ea[1] = CSR_READ_4(sc, ALE_PAR1);
461 		if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
493 	sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
502 	txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
503 	rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
1134 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
1166 		CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1171 		CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1190 		*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
1195 CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
1290 	status = CSR_READ_4(sc, ALE_INTR_STATUS);
1580 	CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
1585 		if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
1592 		if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
1635 	CSR_READ_4(sc, ALE_WOL_CFG);
1694 	reg = CSR_READ_4(sc, ALE_MASTER_CFG);
1758 		reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
1870 	reg = CSR_READ_4(sc, ALE_TXQ_CFG);
1873 	reg = CSR_READ_4(sc, ALE_RXQ_CFG);
1876 	reg = CSR_READ_4(sc, ALE_DMA_CFG);
1906 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
1913 		reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
1973 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
1991 	rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
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