Cross Reference: /src/sys/dev/pci/if

Lines Matching defs:ringidx
5154 	const int ringidx = txring->txr_index;
5171 	AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), TX_DMA_DESC_EN, 0);
5176 		AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRLSW_REG(ringidx), paddr);
5177 		AQ_WRITE_REG(sc, TX_DMA_DESC_BASE_ADDRMSW_REG(ringidx),
5181 		AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx), TX_DMA_DESC_LEN,
5186 		    AQ_READ_REG(sc, TX_DMA_DESC_TAIL_PTR_REG(ringidx));
5187 		AQ_WRITE_REG(sc, TX_DMA_DESC_WRWB_THRESH_REG(ringidx), 0);
5190 		AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(ringidx),
5191 		    AQ_INTR_IRQ_MAP_TX_IRQMAP(ringidx), sc->sc_tx_irq[ringidx]);
5192 		AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_TX_REG(ringidx),
5193 		    AQ_INTR_IRQ_MAP_TX_EN(ringidx), true);
5196 		AQ_WRITE_REG_BIT(sc, TX_DMA_DESC_REG(ringidx),
5200 		AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(ringidx),
5202 		AQ_WRITE_REG_BIT(sc, TDM_DCAD_REG(ringidx),
5214 	const int ringidx = rxring->rxr_index;
5228 	AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), RX_DMA_DESC_EN, 0);
5245 		AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRLSW_REG(ringidx), paddr);
5246 		AQ_WRITE_REG(sc, RX_DMA_DESC_BASE_ADDRMSW_REG(ringidx),
5250 		AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx), RX_DMA_DESC_LEN,
5254 		AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(ringidx),
5256 		AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_BUFSIZE_REG(ringidx),
5259 		AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
5261 		AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
5271 		    RX_DMA_DESC_HEAD_PTR_REG(ringidx), RX_DMA_DESC_HEAD_PTR);
5272 		AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(ringidx),
5278 		AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(ringidx),
5279 		    AQ_INTR_IRQ_MAP_RX_IRQMAP(ringidx), sc->sc_rx_irq[ringidx]);
5280 		AQ_WRITE_REG_BIT(sc, AQ_INTR_IRQ_MAP_RX_REG(ringidx),
5281 		    AQ_INTR_IRQ_MAP_RX_EN(ringidx), 1);
5284 		AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
5286 		AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
5288 		AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
5290 		AQ_WRITE_REG_BIT(sc, RX_DMA_DCAD_REG(ringidx),
5294 		AQ_WRITE_REG_BIT(sc, RX_DMA_DESC_REG(ringidx),
5416 	const int ringidx = txring->txr_index;
5424 	hw_head = AQ_READ_REG_BIT(sc, TX_DMA_DESC_HEAD_PTR_REG(ringidx),
5462 	AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_tx_irq[ringidx]));
5472 	const int ringidx = rxring->rxr_index;
5487 	    RX_DMA_DESC_HEAD_PTR_REG(ringidx), RX_DMA_DESC_HEAD_PTR)) {
5499 	    idx != AQ_READ_REG_BIT(sc, RX_DMA_DESC_HEAD_PTR_REG(ringidx),
5669 		AQ_WRITE_REG(sc, RX_DMA_DESC_TAIL_PTR_REG(ringidx), idx);
5682 	AQ_WRITE_REG(sc, AQ_INTR_STATUS_CLR_REG, __BIT(sc->sc_rx_irq[ringidx]));
5876 	const int ringidx = aq_select_txqueue(sc, m);
5877 	struct aq_txring * const txring = &sc->sc_queue[ringidx].txring;