Lines Matching refs:CSR_READ_4
955 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
963 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
970 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
982 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1046 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1056 byte = CSR_READ_4(sc, BGE_EE_DATA);
1098 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
1110 data = CSR_READ_4(sc, BGE_MI_COMM);
1113 data = CSR_READ_4(sc, BGE_MI_COMM);
1157 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
1169 data = CSR_READ_4(sc, BGE_MI_COMM);
1172 data = CSR_READ_4(sc, BGE_MI_COMM);
1225 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1227 tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1228 rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1970 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1986 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
2000 val = CSR_READ_4(sc, BGE_VCPU_STATUS);
2074 phy_addr += (CSR_READ_4(sc, BGE_SGDIG_STS) &
2077 phy_addr += (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
2117 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
2124 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
2136 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
2144 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
2158 reg = CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL);
2163 mode_ctl = CSR_READ_4(sc, BGE_MODE_CTL);
2171 reg = CSR_READ_4(sc, BGE_TLP_CONTROL_REG +
2181 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
2235 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
2290 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
2438 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2455 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2601 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2725 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2746 val = CSR_READ_4(sc, BGE_RXLP_STATS_ENABLE_MASK);
2763 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2864 CSR_READ_4(sc, BGE_MISC_LOCAL_CTL); /* Flush */
2916 val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2934 dmactl = CSR_READ_4(sc, rdmareg);
2959 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2968 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2973 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2984 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2991 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
3503 misccfg = CSR_READ_4(sc, BGE_MISC_CFG);
3606 else if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL)
3948 macmode = CSR_READ_4(sc, BGE_MAC_MODE);
4209 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4227 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4266 val = CSR_READ_4(sc, BGE_PCIE_LINKCTL);
4280 (CSR_READ_4(sc, BGE_PHY_TEST_CTRL_REG) ==
4297 i = CSR_READ_4(sc, BGE_VCPU_STATUS);
4300 i = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4396 val = CSR_READ_4(sc, BGE_MARB_MODE);
4430 val = CSR_READ_4(sc, BGE_MAC_MODE);
4447 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
4459 v = CSR_READ_4(sc, BGE_TLP_CONTROL_REG);
4755 pcistate = CSR_READ_4(sc, BGE_PCI_PCISTATE);
4811 (void)CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
4815 (void)CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
4849 CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4904 CSR_READ_4(sc, BGE_MAC_STATS +
4917 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4920 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS));
4922 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS));
4929 ucast = CSR_READ_4(sc, BGE_MAC_STATS +
4931 mcast = CSR_READ_4(sc, BGE_MAC_STATS +
4933 bcast = CSR_READ_4(sc, BGE_MAC_STATS +
4942 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4960 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
5614 reg = CSR_READ_4(sc, BGE_CPMU_CTRL);
5619 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_10MB_CLK);
5624 reg = CSR_READ_4(sc, BGE_CPMU_LNK_AWARE_PWRMD);
5629 reg = CSR_READ_4(sc, BGE_CPMU_HST_ACC);
5638 reg = CSR_READ_4(sc, BGE_PCIE_PWRMNG_THRESH);
5644 reg = CSR_READ_4(sc, BGE_PCIE_EIDLE_DELAY);
5655 reg = CSR_READ_4(sc, BGE_PCIE_LINKCTL);
5732 mode = CSR_READ_4(sc, BGE_TX_MODE);
5739 mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5750 mode = CSR_READ_4(sc, BGE_RX_MODE);
5822 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5825 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5858 reg = CSR_READ_4(sc, BGE_CPMU_CTRL);
5872 reg = CSR_READ_4(sc, BGE_CPMU_LSPD_1000MB_CLK);
5912 if (CSR_READ_4(sc, BGE_MAC_STS) &
5916 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
6042 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
6043 const uint32_t status = CSR_READ_4(sc, BGE_RX_STS);
6125 if ((CSR_READ_4(sc, reg) & bit) == 0)
6285 status = CSR_READ_4(sc, BGE_MAC_STS);
6310 status = CSR_READ_4(sc, BGE_MAC_STS);
6333 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK)?
6359 reg = CSR_READ_4(sc, BGE_CPMU_CLCK_STAT) &
6368 reg = CSR_READ_4(sc, BGE_MISC_CFG) &
Indexes created Tue Oct 21 06:10:07 GMT 2025