Lines Matching refs:CSR_WRITE_4
607 CSR_WRITE_4(sc, off, val);
616 CSR_WRITE_4(sc, off, val);
953 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
964 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
966 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
967 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
987 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1041 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1247 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1248 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1697 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1889 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
2121 CSR_WRITE_4(sc, BGE_MODE_CTL, reg | BGE_MODECTL_PCIE_TLPADDR1);
2126 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL1,
2130 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2140 CSR_WRITE_4(sc, BGE_MODE_CTL,
2146 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_PHYCTL5,
2150 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2159 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
2167 CSR_WRITE_4(sc, BGE_MODE_CTL,
2174 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG + BGE_TLP_FTSMAX,
2178 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2184 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg);
2314 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
2368 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
2371 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
2373 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
2377 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
2379 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
2388 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2390 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
2391 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
2393 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
2394 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
2397 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
2400 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
2401 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
2403 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
2404 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2407 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
2408 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
2409 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
2414 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
2415 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
2432 CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
2450 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2451 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2537 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2538 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2539 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2540 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2565 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2567 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2570 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2572 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2584 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2600 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2617 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, 8);
2619 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 8);
2623 CSR_WRITE_4(sc, BGE_STD_REPL_LWM, 4);
2624 CSR_WRITE_4(sc, BGE_JUMBO_REPL_LWM, 4);
2714 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2727 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2734 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2741 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2748 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, val);
2750 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2753 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2757 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2781 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_coal_ticks);
2782 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, tx_coal_ticks);
2783 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_max_coal_bds);
2784 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, tx_max_coal_bds);
2786 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2787 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2789 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
2790 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
2795 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2796 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2797 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, taddr.bge_addr_hi);
2798 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, taddr.bge_addr_lo);
2804 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2805 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi);
2806 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo);
2822 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2826 CSR_WRITE_4(sc, BGE_RBDC_MODE,
2831 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2836 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2872 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2953 CSR_WRITE_4(sc, rdmareg, dmactl |
2958 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2967 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2972 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2996 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
3002 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3005 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
3010 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3017 CSR_WRITE_4(sc, BGE_SDC_MODE, val);
3021 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3025 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3031 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
3034 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3038 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3042 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3045 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
3047 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
3051 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3054 CSR_WRITE_4(sc, BGE_MI_STS, 0);
3061 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
3074 CSR_WRITE_4(sc, BGE_MI_MODE, mimode);
3076 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
3087 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
4225 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4255 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0);
4269 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, val);
4283 CSR_WRITE_4(sc, BGE_PHY_TEST_CTRL_REG,
4291 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4298 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4301 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4397 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4399 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4411 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
4449 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
4460 CSR_WRITE_4(sc, BGE_TLP_CONTROL_REG,
4809 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, rx_ticks);
4813 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, rx_bds);
4947 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
5617 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg);
5622 CSR_WRITE_4(sc, BGE_CPMU_LSPD_10MB_CLK, reg);
5627 CSR_WRITE_4(sc, BGE_CPMU_LNK_AWARE_PWRMD, reg);
5632 CSR_WRITE_4(sc, BGE_CPMU_HST_ACC, reg);
5642 CSR_WRITE_4(sc, BGE_PCIE_PWRMNG_THRESH, reg);
5647 CSR_WRITE_4(sc, BGE_PCIE_EIDLE_DELAY, reg);
5658 CSR_WRITE_4(sc, BGE_PCIE_LINKCTL, reg);
5678 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
5684 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5685 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI,
5824 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5861 CSR_WRITE_4(sc, BGE_CPMU_CTRL, reg);
5877 CSR_WRITE_4(sc, BGE_CPMU_LSPD_1000MB_CLK, reg);
6049 CSR_WRITE_4(sc, BGE_RX_STS, status);
6058 CSR_WRITE_4(sc, BGE_RX_STS, status);
6207 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6208 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6299 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6320 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6371 CSR_WRITE_4(sc, BGE_MISC_CFG, reg);
6374 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
Indexes created Sat Oct 18 08:10:09 GMT 2025