Cross Reference: /src/sys/dev/pci/if

Lines Matching defs:val1
1183 	uint32_t		val1;
1201 		val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
1202 		val1 &= ~BNX_EMAC_MDIO_MODE_AUTO_POLL;
1204 		REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);
1210 	val1 = BNX_MIPHY(phy) | BNX_MIREG(reg) | val |
1213 	REG_WR(sc, BNX_EMAC_MDIO_COMM, val1);
1218 		val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM);
1219 		if (!(val1 & BNX_EMAC_MDIO_COMM_START_BUSY)) {
1225 	if (val1 & BNX_EMAC_MDIO_COMM_START_BUSY) {
1232 		val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
1233 		val1 |= BNX_EMAC_MDIO_MODE_AUTO_POLL;
1235 		REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);
6602 	uint32_t		val1;
6610 	val1 = REG_RD_IND(sc, sc->bnx_shmem_base + BNX_DEV_INFO_BC_REV);
6611 	BNX_PRINTF(sc, "0x%08X : bootcode version\n", val1);
6613 	val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS);
6615 	    val1, BNX_MISC_ENABLE_STATUS_BITS);
6617 	val1 = REG_RD(sc, BNX_DMA_STATUS);
6618 	BNX_PRINTF(sc, "0x%08X : (0x%04X) dma_status\n", val1, BNX_DMA_STATUS);
6620 	val1 = REG_RD(sc, BNX_CTX_STATUS);
6621 	BNX_PRINTF(sc, "0x%08X : (0x%04X) ctx_status\n", val1, BNX_CTX_STATUS);
6623 	val1 = REG_RD(sc, BNX_EMAC_STATUS);
6624 	BNX_PRINTF(sc, "0x%08X : (0x%04X) emac_status\n", val1,
6627 	val1 = REG_RD(sc, BNX_RPM_STATUS);
6628 	BNX_PRINTF(sc, "0x%08X : (0x%04X) rpm_status\n", val1, BNX_RPM_STATUS);
6630 	val1 = REG_RD(sc, BNX_TBDR_STATUS);
6631 	BNX_PRINTF(sc, "0x%08X : (0x%04X) tbdr_status\n", val1,
6634 	val1 = REG_RD(sc, BNX_TDMA_STATUS);
6635 	BNX_PRINTF(sc, "0x%08X : (0x%04X) tdma_status\n", val1,
6638 	val1 = REG_RD(sc, BNX_HC_STATUS);
6639 	BNX_PRINTF(sc, "0x%08X : (0x%04X) hc_status\n", val1, BNX_HC_STATUS);
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