Cross Reference: /src/sys/dev/pci/if

Lines Matching refs:REG_RD
651 	sc->bnx_chipid =  REG_RD(sc, BNX_MISC_ID);
732 	val = REG_RD(sc, BNX_PCICFG_MISC_STATUS);
738 		clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS);
1072 			val = REG_RD(sc, BNX_CTX_CTX_CTRL);
1117 		data = REG_RD(sc, BNX_EMAC_MDIO_MODE);
1121 		REG_RD(sc, BNX_EMAC_MDIO_MODE);
1134 		data = REG_RD(sc, BNX_EMAC_MDIO_COMM);
1138 			data = REG_RD(sc, BNX_EMAC_MDIO_COMM);
1150 		data = REG_RD(sc, BNX_EMAC_MDIO_COMM);
1159 		data = REG_RD(sc, BNX_EMAC_MDIO_MODE);
1163 		REG_RD(sc, BNX_EMAC_MDIO_MODE);
1201 		val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
1205 		REG_RD(sc, BNX_EMAC_MDIO_MODE);
1218 		val1 = REG_RD(sc, BNX_EMAC_MDIO_COMM);
1232 		val1 = REG_RD(sc, BNX_EMAC_MDIO_MODE);
1236 		REG_RD(sc, BNX_EMAC_MDIO_MODE);
1261 	val = REG_RD(sc, BNX_EMAC_MODE);
1367 		val = REG_RD(sc, BNX_NVM_SW_ARB);
1404 		val = REG_RD(sc, BNX_NVM_SW_ARB);
1435 	val = REG_RD(sc, BNX_MISC_CFG);
1448 			val = REG_RD(sc, BNX_NVM_COMMAND);
1478 	val = REG_RD(sc, BNX_MISC_CFG);
1499 	val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE);
1520 	val = REG_RD(sc, BNX_NVM_ACCESS_ENABLE);
1567 		val = REG_RD(sc, BNX_NVM_COMMAND);
1621 		val = REG_RD(sc, BNX_NVM_COMMAND);
1623 			val = REG_RD(sc, BNX_NVM_READ);
1684 		if (REG_RD(sc, BNX_NVM_COMMAND) & BNX_NVM_COMMAND_DONE)
1721 	val = REG_RD(sc, BNX_NVM_CFG1);
2186 		uint32_t val = REG_RD(sc, BNX_MISC_DUAL_MEDIA_CTRL);
3355 			val = REG_RD(sc, BNX_CTX_COMMAND);
3378 				val = REG_RD(sc, BNX_CTX_HOST_PAGE_TBL_CTRL);
3501 	REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS);
3544 		val = REG_RD(sc, BNX_MISC_ENABLE_CLR_BITS);
3548 		val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL);
3551 		REG_RD(sc, BNX_MISC_NEW_CORE_CTL); /* barrier */
3555 			val = REG_RD(sc, BNX_PCICFG_DEVICE_CONTROL);
3574 	val = REG_RD(sc, BNX_MISC_ID);
3579 		REG_RD(sc, BNX_MISC_COMMAND);
3595 			val = REG_RD(sc, BNX_PCICFG_MISC_CONFIG);
3614 	val = REG_RD(sc, BNX_PCI_SWAP_DIAG0);
3698 		val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) |
3710 	val = REG_RD(sc, BNX_MQ_CONFIG);
3731 	val = REG_RD(sc, BNX_TBDR_CONFIG);
3830 		val = REG_RD(sc, BNX_MISC_NEW_CORE_CTL);
3840 		val = REG_RD(sc, BNX_RPM_MGMT_PKT_CTRL) &
3852 	REG_RD(sc, BNX_MISC_ENABLE_SET_BITS);
4291 		val = REG_RD(sc, BNX_MQ_MAP_L2_5);
4956 	REG_RD(sc, BNX_PCICFG_INT_ACK_CMD);
4976 	val = REG_RD(sc, BNX_HC_COMMAND);
5089 	REG_RD(sc, BNX_MISC_ENABLE_SET_BITS);
5451 	if (REG_RD(sc, BNX_EMAC_TX_STATUS) & BNX_EMAC_TX_STATUS_XOFFED)
5502 REG_RD(sc, BNX_PCICFG_MISC_STATUS),
6613 	val1 = REG_RD(sc, BNX_MISC_ENABLE_STATUS_BITS);
6617 	val1 = REG_RD(sc, BNX_DMA_STATUS);
6620 	val1 = REG_RD(sc, BNX_CTX_STATUS);
6623 	val1 = REG_RD(sc, BNX_EMAC_STATUS);
6627 	val1 = REG_RD(sc, BNX_RPM_STATUS);
6630 	val1 = REG_RD(sc, BNX_TBDR_STATUS);
6634 	val1 = REG_RD(sc, BNX_TDMA_STATUS);
6638 	val1 = REG_RD(sc, BNX_HC_STATUS);
6653 		    i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
6654 		    REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
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