Lines Matching refs:REG_WR
1067 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val);
1068 REG_WR(sc, BNX_CTX_CTX_CTRL,
1086 REG_WR(sc, BNX_CTX_DATA_ADR, offset);
1087 REG_WR(sc, BNX_CTX_DATA, ctx_val);
1120 REG_WR(sc, BNX_EMAC_MDIO_MODE, data);
1129 REG_WR(sc, BNX_EMAC_MDIO_COMM, data);
1162 REG_WR(sc, BNX_EMAC_MDIO_MODE, data);
1204 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);
1213 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1);
1235 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1);
1313 REG_WR(sc, BNX_EMAC_MODE, val);
1340 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode);
1365 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_SET2);
1401 REG_WR(sc, BNX_NVM_SW_ARB, BNX_NVM_SW_ARB_ARB_REQ_CLR2);
1436 REG_WR(sc, BNX_MISC_CFG, val | BNX_MISC_CFG_NVM_WR_EN_PCI);
1441 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1442 REG_WR(sc, BNX_NVM_COMMAND,
1479 REG_WR(sc, BNX_MISC_CFG, val & ~BNX_MISC_CFG_NVM_WR_EN);
1501 REG_WR(sc, BNX_NVM_ACCESS_ENABLE,
1523 REG_WR(sc, BNX_NVM_ACCESS_ENABLE,
1557 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1558 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);
1559 REG_WR(sc, BNX_NVM_COMMAND, cmd);
1611 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1612 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);
1613 REG_WR(sc, BNX_NVM_COMMAND, cmd);
1673 REG_WR(sc, BNX_NVM_COMMAND, BNX_NVM_COMMAND_DONE);
1676 REG_WR(sc, BNX_NVM_WRITE, val32);
1677 REG_WR(sc, BNX_NVM_ADDR, offset & BNX_NVM_ADDR_NVM_ADDR_VALUE);
1678 REG_WR(sc, BNX_NVM_COMMAND, cmd);
1772 REG_WR(sc, BNX_NVM_CFG1, flash->config1);
1773 REG_WR(sc, BNX_NVM_CFG2, flash->config2);
1774 REG_WR(sc, BNX_NVM_CFG3, flash->config3);
1775 REG_WR(sc, BNX_NVM_WRITE1, flash->write1);
2814 REG_WR(sc, BNX_RV2P_INSTR_HIGH, *rv2p_code);
2816 REG_WR(sc, BNX_RV2P_INSTR_LOW, *rv2p_code);
2821 REG_WR(sc, BNX_RV2P_PROC1_ADDR_CMD, val);
2824 REG_WR(sc, BNX_RV2P_PROC2_ADDR_CMD, val);
2830 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC1_RESET);
2832 REG_WR(sc, BNX_RV2P_COMMAND, BNX_RV2P_COMMAND_PROC2_RESET);
3351 REG_WR(sc, BNX_CTX_COMMAND, val);
3368 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA0, val |
3372 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_DATA1, val);
3373 REG_WR(sc, BNX_CTX_HOST_PAGE_TBL_CTRL, i |
3399 REG_WR(sc, BNX_CTX_VIRT_ADDR, 0);
3400 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr);
3406 REG_WR(sc, BNX_CTX_VIRT_ADDR, vcid_addr);
3407 REG_WR(sc, BNX_CTX_PAGE_TBL, vcid_addr);
3468 REG_WR(sc, BNX_EMAC_MAC_MATCH0, val);
3473 REG_WR(sc, BNX_EMAC_MAC_MATCH1, val);
3500 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS, 0x5ffffff);
3539 REG_WR(sc, BNX_MISC_ENABLE_CLR_BITS,
3550 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val);
3578 REG_WR(sc, BNX_MISC_COMMAND, BNX_MISC_COMMAND_SW_RESET);
3591 REG_WR(sc, BNX_PCICFG_MISC_CONFIG, val);
3647 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT);
3675 REG_WR(sc, BNX_DMA_CONFIG, val);
3685 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS,
3700 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val);
3721 REG_WR(sc, BNX_MQ_CONFIG, val);
3724 REG_WR(sc, BNX_MQ_KNL_BYP_WIND_START, val);
3725 REG_WR(sc, BNX_MQ_KNL_WIND_END, val);
3728 REG_WR(sc, BNX_RV2P_CONFIG, val);
3734 REG_WR(sc, BNX_TBDR_CONFIG, val);
3767 REG_WR(sc, BNX_EMAC_BACKOFF_SEED, val);
3773 REG_WR(sc, BNX_EMAC_ATTENTION_ENA, BNX_EMAC_ATTENTION_ENA_LINK);
3774 REG_WR(sc, BNX_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3777 REG_WR(sc, BNX_HC_STATUS_ADDR_L, (uint32_t)(sc->status_block_paddr));
3778 REG_WR(sc, BNX_HC_STATUS_ADDR_H,
3782 REG_WR(sc, BNX_HC_STATISTICS_ADDR_L,
3784 REG_WR(sc, BNX_HC_STATISTICS_ADDR_H,
3788 REG_WR(sc, BNX_HC_TX_QUICK_CONS_TRIP, (sc->bnx_tx_quick_cons_trip_int
3790 REG_WR(sc, BNX_HC_RX_QUICK_CONS_TRIP, (sc->bnx_rx_quick_cons_trip_int
3792 REG_WR(sc, BNX_HC_COMP_PROD_TRIP, (sc->bnx_comp_prod_trip_int << 16) |
3794 REG_WR(sc, BNX_HC_TX_TICKS, (sc->bnx_tx_ticks_int << 16) |
3796 REG_WR(sc, BNX_HC_RX_TICKS, (sc->bnx_rx_ticks_int << 16) |
3798 REG_WR(sc, BNX_HC_COM_TICKS, (sc->bnx_com_ticks_int << 16) |
3800 REG_WR(sc, BNX_HC_CMD_TICKS, (sc->bnx_cmd_ticks_int << 16) |
3802 REG_WR(sc, BNX_HC_STATS_TICKS, (sc->bnx_stats_ticks & 0xffff00));
3803 REG_WR(sc, BNX_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3804 REG_WR(sc, BNX_HC_CONFIG,
3809 REG_WR(sc, BNX_HC_COMMAND, BNX_HC_COMMAND_CLR_STAT_NOW);
3832 REG_WR(sc, BNX_MISC_NEW_CORE_CTL, val);
3842 REG_WR(sc, BNX_RPM_MGMT_PKT_CTRL, val);
3847 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS,
3850 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS, BNX_MISC_ENABLE_DEFAULT);
4292 REG_WR(sc, BNX_MQ_MAP_L2_5, val | BNX_MQ_MAP_L2_5_ARM);
4368 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
4506 REG_WR(sc, BNX_PCICFG_STATUS_BIT_SET_CMD,
4510 REG_WR(sc, BNX_PCICFG_STATUS_BIT_CLEAR_CMD,
4517 REG_WR(sc, BNX_EMAC_STATUS, BNX_EMAC_STATUS_LINK_CHANGE);
4819 REG_WR(sc, MB_RX_CID_ADDR + BNX_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
4955 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_MASK_INT);
4970 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID |
4973 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD, BNX_PCICFG_INT_ACK_CMD_INDEX_VALID |
4977 REG_WR(sc, BNX_HC_COMMAND, val | BNX_HC_COMMAND_COAL_NOW);
5031 REG_WR(sc, BNX_EMAC_RX_MTU_SIZE, ether_mtu |
5082 REG_WR(sc, BNX_RV2P_CONFIG, val);
5085 REG_WR(sc, BNX_MISC_ENABLE_SET_BITS,
5359 REG_WR(sc, MB_TX_CID_ADDR + BNX_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5507 REG_WR(sc, BNX_PCICFG_INT_ACK_CMD,
5613 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4),
5636 REG_WR(sc, BNX_EMAC_MULTICAST_HASH0 + (i * 4),
5648 REG_WR(sc, BNX_EMAC_RX_MODE, rx_mode);
5652 REG_WR(sc, BNX_RPM_SORT_USER0, 0x0);
5653 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode);
5654 REG_WR(sc, BNX_RPM_SORT_USER0, sort_mode | BNX_RPM_SORT_USER0_ENA);
Indexes created Fri Oct 17 23:09:53 GMT 2025