Lines Matching refs:CSR_WRITE_4
243 CSR_WRITE_4(sc, ET_PM, pmcfg);
368 CSR_WRITE_4(sc, ET_MII_CMD, 0);
372 CSR_WRITE_4(sc, ET_MII_ADDR, data);
375 CSR_WRITE_4(sc, ET_MII_CMD, ET_MII_CMD_READ);
400 CSR_WRITE_4(sc, ET_MII_CMD, 0);
414 CSR_WRITE_4(sc, ET_MII_CMD, 0);
418 CSR_WRITE_4(sc, ET_MII_ADDR, data);
421 CSR_WRITE_4(sc, ET_MII_CTRL, __SHIFTIN(val, ET_MII_CTRL_VALUE));
441 CSR_WRITE_4(sc, ET_MII_CMD, 0);
515 CSR_WRITE_4(sc, ET_MAC_CTRL, ctrl);
516 CSR_WRITE_4(sc, ET_MAC_CFG2, cfg2);
518 CSR_WRITE_4(sc, ET_MAC_CFG1, cfg1);
670 CSR_WRITE_4(sc, ET_MAC_CFG1,
675 CSR_WRITE_4(sc, ET_SWRST,
680 CSR_WRITE_4(sc, ET_MAC_CFG1,
683 CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
689 CSR_WRITE_4(sc, ET_INTR_MASK, 0xffffffff);
695 CSR_WRITE_4(sc, ET_INTR_MASK, ~intrs);
983 CSR_WRITE_4(sc, ET_LOOPBACK, 0);
986 CSR_WRITE_4(sc, ET_MAC_CFG1,
998 CSR_WRITE_4(sc, ET_MAC_HDX, val);
1001 CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1004 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1007 CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1010 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1037 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1088 CSR_WRITE_4(sc, ET_TIMER, sc->sc_timer);
1207 CSR_WRITE_4(sc, ET_RXDMA_CTRL,
1222 CSR_WRITE_4(sc, ET_TXDMA_CTRL,
1323 CSR_WRITE_4(sc, ET_MULTI_HASH + (i * 4), hash[i]);
1329 CSR_WRITE_4(sc, ET_PKTFILT, pktfilt);
1330 CSR_WRITE_4
1349 CSR_WRITE_4(sc, ET_RXQ_START, 0);
1350 CSR_WRITE_4(sc, ET_RXQ_END, rxq_end);
1351 CSR_WRITE_4(sc, ET_TXQ_START, rxq_end + 1);
1352 CSR_WRITE_4(sc, ET_TXQ_END, ET_INTERN_MEM_END);
1355 CSR_WRITE_4(sc, ET_LOOPBACK, 0);
1358 CSR_WRITE_4(sc, ET_MSI_CFG, 0);
1361 CSR_WRITE_4(sc, ET_TIMER, 0);
1367 CSR_WRITE_4(sc, ET_MMC_CTRL, ET_MMC_CTRL_ENABLE);
1458 CSR_WRITE_4(sc, ET_RX_STATUS_HI, ET_ADDR_HI(rxsd->rxsd_paddr));
1459 CSR_WRITE_4(sc, ET_RX_STATUS_LO, ET_ADDR_LO(rxsd->rxsd_paddr));
1464 CSR_WRITE_4(sc, ET_RXSTAT_HI, ET_ADDR_HI(rxst_ring->rsr_paddr));
1465 CSR_WRITE_4(sc, ET_RXSTAT_LO, ET_ADDR_LO(rxst_ring->rsr_paddr));
1466 CSR_WRITE_4(sc, ET_RXSTAT_CNT, ET_RX_NSTAT - 1);
1467 CSR_WRITE_4(sc, ET_RXSTAT_POS, 0);
1468 CSR_WRITE_4(sc, ET_RXSTAT_MINCNT, ((ET_RX_NSTAT * 15) / 100) - 1);
1478 CSR_WRITE_4(sc, ET_RX_RING1_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1479 CSR_WRITE_4(sc, ET_RX_RING1_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1480 CSR_WRITE_4(sc, ET_RX_RING1_CNT, ET_RX_NDESC - 1);
1481 CSR_WRITE_4(sc, ET_RX_RING1_POS, ET_RX_RING1_POS_WRAP);
1482 CSR_WRITE_4(sc, ET_RX_RING1_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1492 CSR_WRITE_4(sc, ET_RX_RING0_HI, ET_ADDR_HI(rx_ring->rr_paddr));
1493 CSR_WRITE_4(sc, ET_RX_RING0_LO, ET_ADDR_LO(rx_ring->rr_paddr));
1494 CSR_WRITE_4(sc, ET_RX_RING0_CNT, ET_RX_NDESC - 1);
1495 CSR_WRITE_4(sc, ET_RX_RING0_POS, ET_RX_RING0_POS_WRAP);
1496 CSR_WRITE_4(sc, ET_RX_RING0_MINCNT, ((ET_RX_NDESC * 15) / 100) - 1);
1505 CSR_WRITE_4(sc, ET_RX_INTR_NPKTS, sc->sc_rx_intr_npkts);
1506 CSR_WRITE_4(sc, ET_RX_INTR_DELAY, sc->sc_rx_intr_delay);
1527 CSR_WRITE_4(sc, ET_TX_RING_HI, ET_ADDR_HI(tx_ring->tr_paddr));
1528 CSR_WRITE_4(sc, ET_TX_RING_LO, ET_ADDR_LO(tx_ring->tr_paddr));
1529 CSR_WRITE_4(sc, ET_TX_RING_CNT, ET_TX_NDESC - 1);
1534 CSR_WRITE_4(sc, ET_TX_STATUS_HI, ET_ADDR_HI(txsd->txsd_paddr));
1535 CSR_WRITE_4(sc, ET_TX_STATUS_LO, ET_ADDR_LO(txsd->txsd_paddr));
1537 CSR_WRITE_4(sc, ET_TX_READY_POS, 0);
1554 CSR_WRITE_4(sc, ET_MAC_CFG1,
1566 CSR_WRITE_4(sc, ET_IPG, val);
1575 CSR_WRITE_4(sc, ET_MAC_HDX, val);
1578 CSR_WRITE_4(sc, ET_MAC_CTRL, 0);
1581 CSR_WRITE_4(sc, ET_MII_CFG, ET_MII_CFG_CLKRST);
1587 CSR_WRITE_4(sc, ET_MAC_ADDR1, val);
1589 CSR_WRITE_4(sc, ET_MAC_ADDR2, val);
1592 CSR_WRITE_4(sc, ET_MAX_FRMLEN,
1596 CSR_WRITE_4(sc, ET_MAC_CFG1, 0);
1608 CSR_WRITE_4(sc, ET_RXMAC_CTRL, ET_RXMAC_CTRL_WOL_DISABLE);
1614 CSR_WRITE_4(sc, ET_WOL_CRC + (i * 4), 0);
1616 CSR_WRITE_4(sc, ET_WOL_MASK + (i * 4), 0);
1622 CSR_WRITE_4(sc, ET_WOL_SA_LO, val);
1624 CSR_WRITE_4(sc, ET_WOL_SA_HI, val);
1627 CSR_WRITE_4(sc, ET_PKTFILT, 0);
1630 CSR_WRITE_4(sc, ET_UCAST_FILTADDR1, 0);
1631 CSR_WRITE_4(sc, ET_UCAST_FILTADDR2, 0);
1632 CSR_WRITE_4(sc, ET_UCAST_FILTADDR3, 0);
1649 CSR_WRITE_4(sc, ET_RXMAC_MC_SEGSZ, val);
1651 CSR_WRITE_4(sc, ET_RXMAC_MC_WATERMARK, 0);
1654 CSR_WRITE_4(sc, ET_RXMAC_MGT, 0);
1656 CSR_WRITE_4(sc, ET_RXMAC_SPACE_AVL, 0);
1658 CSR_WRITE_4(sc, ET_RXMAC_MGT,
1668 CSR_WRITE_4(sc, ET_PKTFILT, val);
1671 CSR_WRITE_4(sc, ET_RXMAC_CTRL,
1685 CSR_WRITE_4(sc, ET_TXMAC_CTRL, ET_TXMAC_CTRL_FC_DISABLE);
1688 CSR_WRITE_4(sc, ET_TXMAC_FLOWCTRL, 0);
1691 CSR_WRITE_4(sc, ET_TXMAC_CTRL,
1707 CSR_WRITE_4(sc, ET_RXDMA_CTRL, val);
1722 CSR_WRITE_4(sc, ET_TXDMA_CTRL, ET_TXDMA_CTRL_SINGLE_EPKT);
1772 CSR_WRITE_4(sc, ET_RXSTAT_POS, rxstat_pos);
1824 CSR_WRITE_4(sc, rx_ring->rr_posreg, rxring_pos);
1952 CSR_WRITE_4(sc, ET_TX_READY_POS, tx_ready_pos);
Indexes created Tue Oct 21 07:10:13 GMT 2025