Cross Reference: /src/sys/dev/pci/if

Lines Matching refs:CSR_WRITE_4
138 	CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr);
145 	CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, addr);
209 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1174 	CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
1260 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1297 	CSR_WRITE_4(sc, IPW_CSR_INTR, r);
1301 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1340 	CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1504 	CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
1593 	CSR_WRITE_4(sc, IPW_CSR_AUTOINC_ADDR, sc->table1_base);
1743 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, 0);
1745 	CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_STOP_MASTER);
1754 	CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) |
1768 	CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1780 	CSR_WRITE_4(sc, IPW_CSR_RST, CSR_READ_4(sc, IPW_CSR_RST) |
1785 	CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1800 	CSR_WRITE_4(sc, IPW_CSR_RST, 0);
1863 	CSR_WRITE_4(sc, IPW_CSR_IO, IPW_IO_GPIO1_ENABLE | IPW_IO_GPIO3_MASK |
1867 	CSR_WRITE_4(sc, IPW_CSR_INTR_MASK, IPW_INTR_MASK);
1870 	CSR_WRITE_4(sc, IPW_CSR_RST, 0);
1872 	CSR_WRITE_4(sc, IPW_CSR_CTL, CSR_READ_4(sc, IPW_CSR_CTL) |
1883 	CSR_WRITE_4(sc, IPW_CSR_IO, CSR_READ_4(sc, IPW_CSR_IO) |
2216 	CSR_WRITE_4(sc, IPW_CSR_TX_BASE,  sc->tbd_map->dm_segs[0].ds_addr);
2217 	CSR_WRITE_4(sc, IPW_CSR_TX_SIZE,  IPW_NTBD);
2218 	CSR_WRITE_4(sc, IPW_CSR_TX_READ,  0);
2219 	CSR_WRITE_4(sc, IPW_CSR_TX_WRITE, sc->txcur);
2221 	CSR_WRITE_4(sc, IPW_CSR_RX_BASE,  sc->rbd_map->dm_segs[0].ds_addr);
2222 	CSR_WRITE_4(sc, IPW_CSR_RX_SIZE,  IPW_NRBD);
2223 	CSR_WRITE_4(sc, IPW_CSR_RX_READ,  0);
2224 	CSR_WRITE_4(sc, IPW_CSR_RX_WRITE, sc->rxcur);
2226 	CSR_WRITE_4(sc, IPW_CSR_STATUS_BASE, sc->status_map->dm_segs[0].ds_addr);
2266 	CSR_WRITE_4(sc, IPW_CSR_RST, IPW_RST_SW_RESET);
2286 		CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3);
2296 		CSR_WRITE_4(sc, IPW_CSR_INDIRECT_ADDR, offset & ~3);
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