Lines Matching defs:iaq
2118 struct ixl_aq_desc *iaq;
2128 iaq = &iatq.iatq_desc;
2129 iaq->iaq_opcode = htole16(IXL_AQ_OP_SET_VSI_PROMISC);
2131 param = (struct ixl_aq_vsi_promisc_param *)&iaq->iaq_param;
2155 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK))
3604 struct ixl_aq_desc *iaq, iaq_buf;
3607 iaq = &sc->sc_link_state_atq.iatq_desc;
3608 iaq_buf = *iaq;
3614 CLR(iaq->iaq_flags, htole16(IXL_AQ_DD));
3615 ixl_wakeup(sc, iaq);
3621 const struct ixl_aq_desc *iaq)
3631 struct ixl_aq_desc *iaq;
3638 iaq = &iatq->iatq_desc;
3641 !ISSET(iaq->iaq_flags, htole16(IXL_AQ_DD))) {
3642 memset(iaq, 0, sizeof(*iaq));
3643 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS);
3644 param = (struct ixl_aq_link_param *)iaq->iaq_param;
3663 ISSET(iaq->iaq_flags, htole16(IXL_AQ_DD)));
3686 ixl_link_state_update(struct ixl_softc *sc, const struct ixl_aq_desc *iaq)
3692 link_state = ixl_set_link_status_locked(sc, iaq);
3706 ixl_aq_dump(const struct ixl_softc *sc, const struct ixl_aq_desc *iaq,
3716 snprintb(buf, len, IXL_AQ_FLAGS_FMT, le16toh(iaq->iaq_flags));
3718 buf, le16toh(iaq->iaq_opcode));
3720 le16toh(iaq->iaq_datalen), le16toh(iaq->iaq_retval));
3721 device_printf(sc->sc_dev, "cookie %016" PRIx64 "\n", iaq->iaq_cookie);
3723 le32toh(iaq->iaq_param[0]), le32toh(iaq->iaq_param[1]),
3724 le32toh(iaq->iaq_param[2]), le32toh(iaq->iaq_param[3]));
3731 struct ixl_aq_desc *arq, *iaq;
3750 iaq = &arq[cons];
3759 ixl_aq_dump(sc, iaq, "arq event");
3761 switch (iaq->iaq_opcode) {
3763 ixl_link_state_update(sc, iaq);
3767 memset(iaq, 0, sizeof(*iaq));
3895 ixl_wakeup(struct ixl_softc *sc, const struct ixl_aq_desc *iaq)
3940 ixl_atq_poll(struct ixl_softc *sc, struct ixl_aq_desc *iaq, unsigned int tm)
3955 *slot = *iaq;
3977 *iaq = *slot;
3992 struct ixl_aq_desc iaq;
3996 memset(&iaq, 0, sizeof(iaq));
3997 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VERSION);
3999 iaq.iaq_retval = le16toh(23);
4001 if (ixl_atq_poll(sc, &iaq, 2000) != 0)
4003 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK))
4006 fwbuild = le32toh(iaq.iaq_param[1]);
4007 fwver = le32toh(iaq.iaq_param[2]);
4008 apiver = le32toh(iaq.iaq_param[3]);
4067 struct ixl_aq_desc iaq;
4070 memset(&iaq, 0, sizeof(iaq));
4071 iaq.iaq_opcode = htole16(IXL_AQ_OP_CLEAR_PXE_MODE);
4072 iaq.iaq_param[0] = htole32(0x2);
4074 rv = ixl_atq_poll(sc, &iaq, 250);
4081 switch (iaq.iaq_retval) {
4095 struct ixl_aq_desc iaq;
4097 memset(&iaq, 0, sizeof(iaq));
4098 iaq.iaq_opcode = htole16(IXL_AQ_OP_LLDP_STOP_AGENT);
4099 iaq.iaq_param[0] = htole32(IXL_LLDP_SHUTDOWN);
4101 if (ixl_atq_poll(sc, &iaq, 250) != 0) {
4106 switch (iaq.iaq_retval) {
4144 struct ixl_aq_desc iaq;
4152 memset(&iaq, 0, sizeof(iaq));
4153 iaq.iaq_opcode = htole16(IXL_AQ_OP_LIST_FUNC_CAP);
4160 iaq.iaq_flags = htole16(IXL_AQ_BUF |
4162 iaq.iaq_datalen = htole16(caps_size);
4163 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm));
4168 rv = ixl_atq_poll(sc, &iaq, 250);
4178 status = le16toh(iaq.iaq_retval);
4181 caps_size = le16toh(iaq.iaq_datalen);
4192 ncaps = le16toh(iaq.iaq_param[1]);
4207 struct ixl_aq_desc iaq;
4216 memset(&iaq, 0, sizeof(iaq));
4217 iaq.iaq_flags = htole16(IXL_AQ_BUF);
4218 iaq.iaq_opcode = htole16(IXL_AQ_OP_MAC_ADDRESS_READ);
4219 iaq.iaq_datalen = htole16(sizeof(*addrs));
4220 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm));
4225 rv = ixl_atq_poll(sc, &iaq, 250);
4235 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) {
4242 if (!ISSET(iaq.iaq_param[0], htole32(IXL_AQ_MAC_PORT_VALID))) {
4259 struct ixl_aq_desc iaq;
4271 memset(&iaq, 0, sizeof(iaq));
4272 iaq.iaq_flags = htole16(IXL_AQ_BUF |
4274 iaq.iaq_opcode = htole16(IXL_AQ_OP_SWITCH_GET_CONFIG);
4275 iaq.iaq_datalen = htole16(IXL_AQ_BUFLEN);
4276 ixl_aq_dva(&iaq, IXL_DMA_DVA(&idm));
4281 rv = ixl_atq_poll(sc, &iaq, 250);
4291 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) {
4345 struct ixl_aq_desc iaq;
4347 memset(&iaq, 0, sizeof(iaq));
4348 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_EVENT_MASK);
4349 iaq.iaq_param[2] = htole32(IXL_AQ_PHY_EV_MASK &
4353 if (ixl_atq_poll(sc, &iaq, 250) != 0) {
4357 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) {
4368 struct ixl_aq_desc iaq;
4371 memset(&iaq, 0, sizeof(iaq));
4372 iaq.iaq_flags = htole16(IXL_AQ_BUF |
4374 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_GET_ABILITIES);
4375 iaq.iaq_datalen = htole16(IXL_DMA_LEN(idm));
4376 iaq.iaq_param[0] = htole32(IXL_AQ_PHY_REPORT_INIT);
4377 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm));
4382 rv = ixl_atq_poll(sc, &iaq, 250);
4390 return le16toh(iaq.iaq_retval);
4449 struct ixl_aq_desc *iaq;
4454 iaq = &iatq.iatq_desc;
4455 iaq->iaq_opcode = htole16(IXL_AQ_OP_PHY_SET_CONFIG);
4456 param = (struct ixl_aq_phy_param *)&iaq->iaq_param;
4467 error = ixl_atq_poll(sc, iaq, 250);
4474 switch (le16toh(iaq->iaq_retval)) {
4500 struct ixl_aq_desc iaq;
4504 memset(&iaq, 0, sizeof(iaq));
4505 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_LINK_STATUS);
4506 param = (struct ixl_aq_link_param *)iaq.iaq_param;
4509 if (ixl_atq_poll(sc, &iaq, 250) != 0) {
4512 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) {
4517 link = ixl_set_link_status_locked(sc, &iaq);
4529 struct ixl_aq_desc iaq;
4537 memset(&iaq, 0, sizeof(iaq));
4538 iaq.iaq_flags = htole16(IXL_AQ_BUF |
4540 iaq.iaq_opcode = htole16(IXL_AQ_OP_GET_VSI_PARAMS);
4541 iaq.iaq_datalen = htole16(IXL_DMA_LEN(vsi));
4542 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi));
4544 param = (struct ixl_aq_vsi_param *)iaq.iaq_param;
4550 rv = ixl_atq_poll(sc, &iaq, 250);
4559 switch (le16toh(iaq.iaq_retval)) {
4570 reply = (struct ixl_aq_vsi_reply *)iaq.iaq_param;
4582 struct ixl_aq_desc iaq;
4614 memset(&iaq, 0, sizeof(iaq));
4615 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD |
4617 iaq.iaq_opcode = htole16(IXL_AQ_OP_UPD_VSI_PARAMS);
4618 iaq.iaq_datalen = htole16(IXL_DMA_LEN(vsi));
4619 ixl_aq_dva(&iaq, IXL_DMA_DVA(vsi));
4621 param = (struct ixl_aq_vsi_param *)iaq.iaq_param;
4627 rv = ixl_atq_poll(sc, &iaq, 250);
4636 switch (le16toh(iaq.iaq_retval)) {
4685 struct ixl_aq_desc *iaq;
4693 iaq = &iatq.iatq_desc;
4701 iaq->iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD |
4703 iaq->iaq_opcode = htole16(IXL_AQ_OP_RSS_SET_KEY);
4704 iaq->iaq_datalen = htole16(datalen);
4706 param = (struct ixl_aq_rss_key_param *)iaq->iaq_param;
4723 ixl_aq_dva(iaq, IXL_DMA_DVA(idm));
4737 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) {
4749 struct ixl_aq_desc *iaq;
4757 iaq = &iatq.iatq_desc;
4762 iaq->iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD |
4764 iaq->iaq_opcode = htole16(IXL_AQ_OP_RSS_SET_LUT);
4765 iaq->iaq_datalen = htole16(dmalen);
4770 ixl_aq_dva(iaq, IXL_DMA_DVA(idm));
4772 param = (struct ixl_aq_rss_lut_param *)iaq->iaq_param;
4791 if (iaq->iaq_retval != htole16(IXL_AQ_RC_OK)) {
4946 struct ixl_aq_desc iaq;
4948 memset(&iaq, 0, sizeof(iaq));
4949 iaq.iaq_opcode = htole16(IXL_AQ_OP_PHY_RESTART_AN);
4950 iaq.iaq_param[0] =
4953 if (ixl_atq_poll(sc, &iaq, 250) != 0) {
4957 if (iaq.iaq_retval != htole16(IXL_AQ_RC_OK)) {
4969 struct ixl_aq_desc iaq;
4973 memset(&iaq, 0, sizeof(iaq));
4974 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD);
4975 iaq.iaq_opcode = htole16(IXL_AQ_OP_ADD_MACVLAN);
4976 iaq.iaq_datalen = htole16(sizeof(*elem));
4977 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch));
4979 param = (struct ixl_aq_add_macvlan *)&iaq.iaq_param;
4991 if (ixl_atq_poll(sc, &iaq, 250) != 0) {
4995 switch (le16toh(iaq.iaq_retval)) {
5019 struct ixl_aq_desc iaq;
5023 memset(&iaq, 0, sizeof(iaq));
5024 iaq.iaq_flags = htole16(IXL_AQ_BUF | IXL_AQ_RD);
5025 iaq.iaq_opcode = htole16(IXL_AQ_OP_REMOVE_MACVLAN);
5026 iaq.iaq_datalen = htole16(sizeof(*elem));
5027 ixl_aq_dva(&iaq, IXL_DMA_DVA(&sc->sc_scratch));
5029 param = (struct ixl_aq_remove_macvlan *)&iaq.iaq_param;
5041 if (ixl_atq_poll(sc, &iaq, 250) != 0) {
5045 switch (le16toh(iaq.iaq_retval)) {
5301 struct ixl_aq_desc *arq, *iaq;
5315 iaq = &arq[prod];
5332 iaq->iaq_flags = htole16(IXL_AQ_BUF |
5335 iaq->iaq_opcode = 0;
5336 iaq->iaq_datalen = htole16(aqb->aqb_size);
5337 iaq->iaq_retval = 0;
5338 iaq->iaq_cookie = 0;
5339 iaq->iaq_param[0] = 0;
5340 iaq->iaq_param[1] = 0;
5341 ixl_aq_dva(iaq, aqb->aqb_map->dm_segs[0].ds_addr);
5707 ixl_set_link_status_locked(struct ixl_softc *sc, const struct ixl_aq_desc *iaq)
5717 status = (const struct ixl_aq_link_status *)iaq->iaq_param;
6809 struct ixl_aq_desc iaq;
6811 memset(&iaq, 0, sizeof(iaq));
6812 iaq.iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_REG_READ);
6813 iaq.iaq_param[1] = htole32(reg);
6815 if (ixl_atq_poll(sc, &iaq, 250) != 0)
6818 switch (htole16(iaq.iaq_retval)) {
6830 *rv = htole32(iaq.iaq_param[3]);
6864 struct ixl_aq_desc iaq;
6866 memset(&iaq, 0, sizeof(iaq));
6867 iaq.iaq_opcode = htole16(IXL_AQ_OP_RX_CTL_REG_WRITE);
6868 iaq.iaq_param[1] = htole32(reg);
6869 iaq.iaq_param[3] = htole32(value);
6871 if (ixl_atq_poll(sc, &iaq, 250) != 0)
6874 switch (htole16(iaq.iaq_retval)) {
6916 struct ixl_aq_desc iaq;
6923 memset(&iaq, 0, sizeof(iaq));
6924 iaq.iaq_opcode = htole16(IXL_AQ_OP_REQUEST_RESOURCE);
6926 param = (struct ixl_aq_req_resource_param *)&iaq.iaq_param;
6934 rv = ixl_atq_poll(sc, &iaq, 250);
6939 switch (le16toh(iaq.iaq_retval)) {
6956 struct ixl_aq_desc iaq;
6963 memset(&iaq, 0, sizeof(iaq));
6964 iaq.iaq_opcode = htole16(IXL_AQ_OP_RELEASE_RESOURCE);
6966 param = (struct ixl_aq_rel_resource_param *)&iaq.iaq_param;
6969 rv = ixl_atq_poll(sc, &iaq, 250);
6974 switch (le16toh(iaq.iaq_retval)) {
7033 struct ixl_aq_desc iaq;
7043 memset(&iaq, 0, sizeof(iaq));
7044 iaq.iaq_opcode = htole16(IXL_AQ_OP_NVM_READ);
7045 iaq.iaq_flags = htole16(IXL_AQ_BUF |
7047 iaq.iaq_datalen = htole16(len);
7048 ixl_aq_dva(&iaq, IXL_DMA_DVA(idm));
7050 param = (struct ixl_aq_nvm_param *)iaq.iaq_param;
7061 rv = ixl_atq_poll(sc, &iaq, 250);
7070 switch (le16toh(iaq.iaq_retval)) {
Indexes created Tue Sep 30 11:09:46 GMT 2025