Cross Reference: /src/sys/dev/pci/if

Lines Matching defs:rtwn_bb_read
184 #define rtwn_bb_read	rtwn_read_4
841 	reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
843 		reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
858 	if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
859 		val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
861 		val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
1378 			reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1382 			reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1415 		reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1423 		reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
2707 		reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO);
2711 		reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO);
2715 		reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
2719 		reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
2723 		reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
2727 		reg = rtwn_bb_read(sc, 0xe74);
2730 		reg = rtwn_bb_read(sc, 0xe78);
2733 		reg = rtwn_bb_read(sc, 0xe7c);
2736 		reg = rtwn_bb_read(sc, 0xe80);
2739 		reg = rtwn_bb_read(sc, 0xe88);
2751 	if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
2780 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2784 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2789 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2794 		reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2798 		reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2820 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2922 		reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
2925 		reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2931 		reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
2936 		reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
3126 		    rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
3128 		    rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
3131 		reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM);
3135 		reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF);
3140 		    rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
3143 		reg = rtwn_bb_read(sc, 0x818);
3157 		    rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
3159 		    rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
3162 		    rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
3356 	reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
3359 	reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
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