Lines Matching refs:sc_if
412 struct sk_if_softc *sc_if = device_private(dev);
417 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
420 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
421 SK_XM_READ_2(sc_if, XM_PHY_DATA);
422 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
425 if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
431 aprint_error_dev(sc_if->sk_dev,
437 *val = SK_XM_READ_2(sc_if, XM_PHY_DATA);
444 struct sk_if_softc *sc_if = device_private(dev);
449 SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
451 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
456 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n");
460 SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
463 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
468 aprint_error_dev(sc_if->sk_dev, "phy write timed out\n");
478 struct sk_if_softc *sc_if = ifp->if_softc;
479 struct mii_data *mii = &sc_if->sk_mii;
487 if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
489 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
491 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
498 struct sk_if_softc *sc_if = device_private(dev);
503 (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
504 sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
510 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
515 data = SK_YU_READ_2(sc_if, YUKON_SMICR);
521 aprint_error_dev(sc_if->sk_dev, "phy failed to come ready\n");
528 *val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
539 struct sk_if_softc *sc_if = device_private(dev);
545 SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
546 SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
551 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY))
557 device_xname(sc_if->sk_dev));
595 sk_setfilt(struct sk_if_softc *sc_if, void *addrv, int slot)
600 SK_XM_WRITE_2(sc_if, base, *(uint16_t *)(&addr[0]));
601 SK_XM_WRITE_2(sc_if, base + 2, *(uint16_t *)(&addr[2]));
602 SK_XM_WRITE_2(sc_if, base + 4, *(uint16_t *)(&addr[4]));
606 sk_setmulti(struct sk_if_softc *sc_if)
608 struct sk_softc *sc = sc_if->sk_softc;
609 struct ifnet *ifp= &sc_if->sk_ethercom.ec_if;
612 struct ethercom *ec = &sc_if->sk_ethercom;
621 sk_setfilt(sc_if, (void *)&dummy, i);
623 SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
624 SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
629 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
630 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
631 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
632 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
661 sk_setfilt(sc_if, enm->enm_addrlo, i);
688 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH |
690 SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
691 SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
696 SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
697 SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
698 SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
699 SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
705 sk_init_rx_ring(struct sk_if_softc *sc_if)
707 struct sk_chain_data *cd = &sc_if->sk_cdata;
708 struct sk_ring_data *rd = sc_if->sk_rdata;
719 htole32(SK_RX_RING_ADDR(sc_if, 0));
723 htole32(SK_RX_RING_ADDR(sc_if, i+1));
728 if (sk_newbuf(sc_if, i, NULL,
729 sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) {
730 aprint_error_dev(sc_if->sk_dev,
735 sc_if->sk_cdata.sk_rx_prod = 0;
736 sc_if->sk_cdata.sk_rx_cons = 0;
742 sk_init_tx_ring(struct sk_if_softc *sc_if)
744 struct sk_chain_data *cd = &sc_if->sk_cdata;
745 struct sk_ring_data *rd = sc_if->sk_rdata;
748 memset(sc_if->sk_rdata->sk_tx_ring, 0,
756 htole32(SK_TX_RING_ADDR(sc_if, 0));
760 htole32(SK_TX_RING_ADDR(sc_if, i+1));
764 sc_if->sk_cdata.sk_tx_prod = 0;
765 sc_if->sk_cdata.sk_tx_cons = 0;
766 sc_if->sk_cdata.sk_tx_cnt = 0;
768 SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT,
775 sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m,
787 aprint_error_dev(sc_if->sk_dev,
793 buf = sk_jalloc(sc_if);
797 "dropped!\n", sc_if->sk_ethercom.ec_if.if_xname));
803 MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if);
817 c = &sc_if->sk_cdata.sk_rx_chain[i];
822 - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)));
825 SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
835 sk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
837 struct sk_softc *sc = sc_if->sk_softc;
864 BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) {
871 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map,
879 sc_if->sk_cdata.sk_jumbo_buf = (void *)kva;
880 DPRINTFN(1,("sk_jumbo_buf = %p\n", sc_if->sk_cdata.sk_jumbo_buf));
882 LIST_INIT(&sc_if->sk_jfree_listhead);
883 LIST_INIT(&sc_if->sk_jinuse_listhead);
884 mutex_init(&sc_if->sk_jpool_mtx, MUTEX_DEFAULT, IPL_NET);
890 ptr = sc_if->sk_cdata.sk_jumbo_buf;
892 sc_if->sk_cdata.sk_jslots[i] = ptr;
898 LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
901 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead,
909 sc_if->sk_cdata.sk_rx_jumbo_map);
913 sc_if->sk_cdata.sk_rx_jumbo_map);
933 sk_jalloc(struct sk_if_softc *sc_if)
937 mutex_enter(&sc_if->sk_jpool_mtx);
938 entry = LIST_FIRST(&sc_if->sk_jfree_listhead);
941 mutex_exit(&sc_if->sk_jpool_mtx);
946 LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
947 mutex_exit(&sc_if->sk_jpool_mtx);
948 return sc_if->sk_cdata.sk_jslots[entry->slot];
994 struct sk_if_softc *sc_if = ifp->if_softc;
998 if ((rc = mii_mediachg(&sc_if->sk_mii)) == ENXIO)
1004 sk_promisc(struct sk_if_softc *sc_if, int on)
1006 struct sk_softc *sc = sc_if->sk_softc;
1010 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
1012 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
1018 SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
1021 SK_YU_SETBIT_2(sc_if, YUKON_RCR,
1025 aprint_error_dev(sc_if->sk_dev, "Can't set promisc for %d\n",
1034 struct sk_if_softc *sc_if = ifp->if_softc;
1055 if ((ifp->if_flags ^ sc_if->sk_if_flags) == IFF_PROMISC) {
1056 sk_promisc(sc_if, ifp->if_flags & IFF_PROMISC);
1057 sk_setmulti(sc_if);
1062 sc_if->sk_if_flags = ifp->if_flags;
1076 sk_setmulti(sc_if);
1202 struct sk_if_softc *sc_if = device_private(self);
1203 struct mii_data *mii = &sc_if->sk_mii;
1216 sc_if->sk_dev = self;
1217 sc_if->sk_port = sa->skc_port;
1218 sc_if->sk_softc = sc;
1219 sc->sk_if[sa->skc_port] = sc_if;
1222 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
1224 sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
1226 DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
1237 if (! ether_getaddr(self, sc_if->sk_enaddr)) {
1239 sc_if->sk_enaddr[i] = sk_win_read_1(sc,
1244 ether_sprintf(sc_if->sk_enaddr));
1259 sc_if->sk_rx_ramstart = val;
1261 sc_if->sk_rx_ramend = val - 1;
1262 sc_if->sk_tx_ramstart = val;
1264 sc_if->sk_tx_ramend = val - 1;
1269 val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
1271 sc_if->sk_rx_ramstart = val;
1273 sc_if->sk_rx_ramend = val - 1;
1274 sc_if->sk_tx_ramstart = val;
1276 sc_if->sk_tx_ramend = val - 1;
1281 sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
1282 sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
1285 sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
1286 switch (sc_if->sk_phytype) {
1288 sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
1291 sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
1294 sc_if->sk_phyaddr = SK_PHYADDR_MARV;
1298 sc_if->sk_phytype);
1310 aprint_error_dev(sc_if->sk_dev,
1318 &sc_if->sk_ring_map)) {
1319 aprint_error_dev(sc_if->sk_dev, "can't create dma map\n");
1325 if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva,
1327 aprint_error_dev(sc_if->sk_dev, "can't load dma map\n");
1328 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
1336 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
1338 SIMPLEQ_INIT(&sc_if->sk_txmap_head);
1340 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
1344 aprint_error_dev(sc_if->sk_dev,
1346 bus_dmamap_unload(sc->sc_dmatag, sc_if->sk_ring_map);
1347 bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
1356 SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link);
1359 sc_if->sk_rdata = (struct sk_ring_data *)kva;
1360 memset(sc_if->sk_rdata, 0, sizeof(struct sk_ring_data));
1362 ifp = &sc_if->sk_ethercom.ec_if;
1364 if (sk_alloc_jumbo_mem(sc_if)) {
1369 sc_if->sk_ethercom.ec_capabilities = ETHERCAP_VLAN_MTU
1372 ifp->if_softc = sc_if;
1382 strlcpy(ifp->if_xname, device_xname(sc_if->sk_dev), IFNAMSIZ);
1389 sk_unreset_xmac(sc_if);
1394 sk_unreset_yukon(sc_if);
1421 sc_if->sk_ethercom.ec_mii = mii;
1426 aprint_error_dev(sc_if->sk_dev, "no PHY found!\n");
1432 callout_init(&sc_if->sk_tick_ch, 0);
1433 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
1443 ether_ifattach(ifp, sc_if->sk_enaddr);
1838 sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, uint32_t *txidx)
1840 struct sk_softc *sc = sc_if->sk_softc;
1849 entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head);
1881 if ((SK_TX_RING_CNT - (sc_if->sk_cdata.sk_tx_cnt + cnt)) < 2) {
1885 f = &sc_if->sk_rdata->sk_tx_ring[frag];
1898 sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
1899 SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
1901 sc_if->sk_cdata.sk_tx_map[cur] = entry;
1902 sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
1906 SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs,
1909 sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |=
1913 SK_CDTXSYNC(sc_if, *txidx, 1,
1916 sc_if->sk_cdata.sk_tx_cnt += cnt;
1923 desc = &sc_if->sk_rdata->sk_tx_ring[idx];
1939 struct sk_if_softc *sc_if = ifp->if_softc;
1940 struct sk_softc *sc = sc_if->sk_softc;
1942 uint32_t idx = sc_if->sk_cdata.sk_tx_prod;
1946 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf));
1948 while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
1958 if (sk_encap(sc_if, m_head, &idx)) {
1977 if (idx != sc_if->sk_cdata.sk_tx_prod) {
1978 sc_if->sk_cdata.sk_tx_prod = idx;
1979 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
1990 struct sk_if_softc *sc_if = ifp->if_softc;
1996 sk_txeof(sc_if);
1997 if (sc_if->sk_cdata.sk_tx_cnt != 0) {
1998 aprint_error_dev(sc_if->sk_dev, "watchdog timeout\n");
2010 struct sk_if_softc *sc_if = (struct sk_if_softc *)v;
2011 struct sk_softc *sc = sc_if->sk_softc;
2012 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2029 sk_rxeof(struct sk_if_softc *sc_if)
2031 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2039 i = sc_if->sk_cdata.sk_rx_prod;
2047 SK_CDRXSYNC(sc_if, cur,
2050 sk_ctl = le32toh(sc_if->sk_rdata->sk_rx_ring[cur].sk_ctl);
2053 SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD);
2054 sc_if->sk_cdata.sk_rx_prod = i;
2058 cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur];
2059 cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur];
2060 dmamap = sc_if->sk_cdata.sk_rx_jumbo_map;
2062 bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0,
2070 sc_if->sk_cdata.sk_rx_map[cur] = 0;
2076 sk_newbuf(sc_if, cur, m, dmamap);
2087 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) {
2091 sk_newbuf(sc_if, cur, m, dmamap);
2093 aprint_error_dev(sc_if->sk_dev, "no receive "
2111 sk_txeof(struct sk_if_softc *sc_if)
2113 struct sk_softc *sc = sc_if->sk_softc;
2115 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2125 idx = sc_if->sk_cdata.sk_tx_cons;
2126 while (idx != sc_if->sk_cdata.sk_tx_prod) {
2127 SK_CDTXSYNC(sc_if, idx, 1,
2130 cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
2137 SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD);
2142 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
2143 entry = sc_if->sk_cdata.sk_tx_map[idx];
2149 SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry,
2151 sc_if->sk_cdata.sk_tx_map[idx] = NULL;
2153 m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
2154 sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
2156 sc_if->sk_cdata.sk_tx_cnt--;
2159 if (sc_if->sk_cdata.sk_tx_cnt == 0)
2162 CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
2164 if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2)
2167 sc_if->sk_cdata.sk_tx_cons = idx;
2173 struct sk_if_softc *sc_if = xsc_if;
2174 struct mii_data *mii = &sc_if->sk_mii;
2175 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2183 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2184 sk_intr_bcom(sc_if);
2196 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
2201 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2206 SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2207 SK_XM_READ_2(sc_if, XM_ISR);
2210 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2212 callout_stop(&sc_if->sk_tick_ch);
2216 sk_intr_bcom(struct sk_if_softc *sc_if)
2218 struct mii_data *mii = &sc_if->sk_mii;
2219 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2225 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB);
2231 sk_xmac_miibus_readreg(sc_if->sk_dev,
2235 sk_init_xmac(sc_if);
2241 sk_xmac_miibus_readreg(sc_if->sk_dev,
2244 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
2247 SK_IF_WRITE_1(sc_if, 0,
2249 sc_if->sk_link = 0;
2251 sk_xmac_miibus_writereg(sc_if->sk_dev,
2254 sc_if->sk_link = 1;
2256 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2262 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2266 SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB | XM_MMUCMD_RX_ENB);
2270 sk_intr_xmac(struct sk_if_softc *sc_if)
2272 uint16_t status = SK_XM_READ_2(sc_if, XM_ISR);
2276 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
2278 SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
2279 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2283 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2288 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
2291 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
2295 sk_intr_yukon(struct sk_if_softc *sc_if)
2302 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2401 sk_unreset_xmac(struct sk_if_softc *sc_if)
2403 struct sk_softc *sc = sc_if->sk_softc;
2413 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
2417 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2420 sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
2427 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2434 if (sc_if->sk_port == SK_PORT_A)
2441 SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
2443 sk_xmac_miibus_writereg(sc_if->sk_dev,
2446 sk_xmac_miibus_writereg(sc_if->sk_dev,
2455 sk_xmac_miibus_readreg(sc_if->sk_dev,
2459 sk_xmac_miibus_writereg(sc_if->sk_dev,
2469 sk_init_xmac(struct sk_if_softc *sc_if)
2471 struct sk_softc *sc = sc_if->sk_softc;
2472 struct ifnet *ifp = &sc_if->sk_ethercom.ec_if;
2474 sk_unreset_xmac(sc_if);
2477 SK_XM_WRITE_2(sc_if, XM_PAR0,
2478 *(uint16_t *)(&sc_if->sk_enaddr[0]));
2479 SK_XM_WRITE_2(sc_if, XM_PAR1,
2480 *(uint16_t *)(&sc_if->sk_enaddr[2]));
2481 SK_XM_WRITE_2(sc_if, XM_PAR2,
2482 *(uint16_t *)(&sc_if->sk_enaddr[4]));
2483 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
2486 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
2488 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
2491 SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2493 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
2496 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
2499 SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
2515 SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES |
2520 SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2522 SK_XM_CLRBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
2528 SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
2531 sk_setmulti(sc_if);
2534 SK_XM_READ_2(sc_if, XM_ISR);
2535 if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
2536 SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
2538 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2541 switch (sc_if->sk_xmac_rev) {
2570 sc_if->sk_link = 1;
2574 sk_unreset_yukon(struct sk_if_softc *sc_if)
2580 CSR_READ_4(sc_if->sk_softc, SK_CSR)));
2582 sc = sc_if->sk_softc;
2592 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
2596 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2598 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_CLEAR);
2599 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
2608 switch (sc_if->sk_softc->sk_pmd) {
2622 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
2624 SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
2625 SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
2629 SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
2633 sk_init_yukon(struct sk_if_softc *sc_if)
2639 sk_unreset_yukon(sc_if);
2643 SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
2646 reg = SK_YU_READ_2(sc_if, YUKON_PAR);
2653 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2658 SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
2662 SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_UFLEN | YU_RCR_MUFLEN |
2667 SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
2672 SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) |
2680 SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4,
2681 sc_if->sk_enaddr[i * 2] |
2682 sc_if->sk_enaddr[i * 2 + 1] << 8);
2686 reg = sk_win_read_2(sc_if->sk_softc,
2687 SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
2688 SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
2693 sk_setmulti(sc_if);
2697 SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
2698 SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
2699 SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
2702 SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
2703 SK_IF_WRITE_4(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_OPERATION_ON);
2706 SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
2707 SK_IF_WRITE_4(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
2719 struct sk_if_softc *sc_if = ifp->if_softc;
2720 struct sk_softc *sc = sc_if->sk_softc;
2721 struct mii_data *mii = &sc_if->sk_mii;
2739 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
2740 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
2744 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
2748 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
2757 sk_init_xmac(sc_if);
2762 sk_init_yukon(sc_if);
2772 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
2773 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
2774 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
2776 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
2777 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
2778 SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
2782 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
2786 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
2787 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
2788 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
2789 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
2790 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
2791 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
2793 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
2794 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
2795 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
2796 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
2797 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
2798 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
2799 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
2802 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
2803 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
2804 SK_RX_RING_ADDR(sc_if, 0));
2805 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
2807 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
2808 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
2809 SK_TX_RING_ADDR(sc_if, 0));
2810 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
2813 if (sk_init_rx_ring(sc_if) == ENOBUFS) {
2814 aprint_error_dev(sc_if->sk_dev, "initialization failed: no "
2821 if (sk_init_tx_ring(sc_if) == ENOBUFS) {
2822 aprint_error_dev(sc_if->sk_dev, "initialization failed: no "
2850 if (sc_if->sk_port == SK_PORT_A)
2860 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
2864 SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
2865 SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
2870 uint16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
2876 SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
2882 callout_reset(&sc_if->sk_tick_ch, hz, sk_tick, sc_if);
2892 struct sk_if_softc *sc_if = ifp->if_softc;
2893 struct sk_softc *sc = sc_if->sk_softc;
2898 callout_stop(&sc_if->sk_tick_ch);
2900 if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
2905 if (sc_if->sk_port == SK_PORT_A) {
2916 SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
2919 SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL,
2921 SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
2926 SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
2927 SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
2930 SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
2931 SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET |SK_RBCTL_OFF);
2932 SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
2933 SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
2934 SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
2935 SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2936 SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
2937 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
2938 SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
2941 if (sc_if->sk_port == SK_PORT_A)
2947 SK_XM_READ_2(sc_if, XM_ISR);
2948 SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
2952 m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
2953 sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
2957 m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
2958 sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
2995 struct sk_if_softc *sc_if = device_private(dv);
2997 sk_init_yukon(sc_if);
Indexes created Mon Oct 20 11:09:49 GMT 2025