Cross Reference: /src/sys/dev/pci/if

Lines Matching refs:CSR_READ_4
244 	ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
268 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
277 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
285 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
296 		    device_xname(sc->sc_dev), CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
307 		if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
1155 	intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1225 	if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1229 		if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1267 	if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1277 	rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK;
1309 	cacheline = PCI_CACHELINE(CSR_READ_4(sc, PCI_BHLC_REG));
1317 	if (CSR_READ_4(sc, PCI_COMMAND_STATUS_REG)
1334 				    CSR_READ_4(sc, PCI_COMMAND_STATUS_REG)
2158 	if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
2415 	prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2647 		media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2657 		media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
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