Cross Reference: /src/sys/dev/pci/if

Lines Matching refs:CSR_WRITE_4
363 		CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
413 		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
432 		CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
452 	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
454 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
470 	CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(uint32_t *)(cmd));
473 		CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
477 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
532 		CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
1042 	CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
1084 		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1085 		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1112 		CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1113 		CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1156 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1197 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1213 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1226 		CSR_WRITE_4(sc, 0x600, 0);
1227 		CSR_WRITE_4(sc, 0x604, 0);
1228 		CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1259 	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1262 	CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1299 	CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD);
1333 			CSR_WRITE_4(sc, PCI_COMMAND_STATUS_REG,
1358 	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1363 	CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA |
1382 	CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1383 	CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1408 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1411 	CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1412 	CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, TI_CDGIBADDR(sc));
1428 	CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1438 		CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1440 	CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1441 	CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1514 	CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1556 		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1559 		CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1560 	CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1561 	CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1562 	CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1563 	CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1564 	CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1567 	CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1568 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2035 		CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
2061 			CSR_WRITE_4(sc, TI_WINBASE,
2064 			CSR_WRITE_4(sc, TI_WINBASE,
2067 			CSR_WRITE_4(sc, TI_WINBASE,
2070 			CSR_WRITE_4(sc, TI_WINBASE,
2163 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2176 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2252 			CSR_WRITE_4(sc, TI_WINBASE,
2255 			CSR_WRITE_4(sc, TI_WINBASE,
2258 			CSR_WRITE_4(sc, TI_WINBASE,
2261 			CSR_WRITE_4(sc, TI_WINBASE,
2442 	CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2481 	CSR_WRITE_4(sc, TI_GCR_IFINDEX, device_unit(sc->sc_dev)); /* ??? */
2486 	CSR_WRITE_4(sc, TI_GCR_IFMTU, tmp);
2492 	CSR_WRITE_4(sc, TI_GCR_PAR0, (m[0] << 8) | m[1]);
2493 	CSR_WRITE_4(sc, TI_GCR_PAR1, (m[2] << 24) | (m[3] << 16)
2529 	CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2539 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2575 		CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF | TI_GLNK_1000MB |
2578 		CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB | TI_LNK_10MB |
2587 			CSR_WRITE_4(sc, TI_GCR_GLINK,
2591 			CSR_WRITE_4(sc, TI_GCR_GLINK,
2595 		CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2603 		CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2604 		CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB | TI_LNK_PREF);
2813 	CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
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