Cross Reference: /src/sys/dev/pci/if

Lines Matching defs:CSR_WRITE_1
264 #define CSR_WRITE_1(sc, reg, val)	\
275 	CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) | (x))
282 	CSR_WRITE_1((sc), (reg), CSR_READ_1((sc), (reg)) & ~(x))
380 	CSR_WRITE_1(sc, VGE_EEADDR, addr);
411 	CSR_WRITE_1(sc, VGE_MIICMD, 0);
432 	CSR_WRITE_1(sc, VGE_MIICMD, 0);
433 	CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
449 	CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
480 	CSR_WRITE_1(sc, VGE_MIIADDR, reg);
518 	CSR_WRITE_1(sc, VGE_MIIADDR, reg);
557 	CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
559 		CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
563 	CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | VGE_CAMADDR_AVSEL);
565 		CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
567 	CSR_WRITE_1(sc, VGE_CAMADDR, 0);
589 	CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE | sc->sc_camidx);
593 		CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
624 	CSR_WRITE_1(sc, VGE_CAMADDR, 0);
721 	CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
731 		CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
1407 		CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1465 	CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1487 			CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1488 			CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1502 	CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1726 		CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1776 		CSR_WRITE_1(sc, VGE_PAR0 + i, sc->sc_eaddr[i]);
1813 	CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1814 	CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1820 	CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST | VGE_RXCTL_RX_GIANT);
1845 	CSR_WRITE_1(sc, VGE_CRS2, 0x8B);
1850 	CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
1851 	CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
1852 	CSR_WRITE_1(sc, VGE_CRS0,
1871 	CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE);
1875 	CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */
1878 	CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
1879 	CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD);
1884 	CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */
1897 		CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1906 		CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1971 	CSR_WRITE_1(sc, VGE_DIAGCTL, dctl);
2062 	CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2063 	CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
2066 	CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
2188 	CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2192 	CSR_WRITE_1(sc, VGE_PWRSTAT, val);
2198 	CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL);
2200 	CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F);
2201 	CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM |
2204 	CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF);
2205 	CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF);
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