Cross Reference: /src/sys/dev/pci/if

Lines Matching refs:CSR_WRITE_2
343 	CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |
366 	CSR_WRITE_2(sc, VTE_MMWD, val);
367 	CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |
419 		CSR_WRITE_2(sc, VTE_MRICR, val);
427 		CSR_WRITE_2(sc, VTE_MTICR, val);
814 		CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);
890 	CSR_WRITE_2(sc, VTE_MCR0, mcr);
976 	CSR_WRITE_2(sc, VTE_MIER, 0);
996 		CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1181 		CSR_WRITE_2(sc, VTE_MRDCR, prog |
1213 	CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
1226 	CSR_WRITE_2(sc, VTE_MACSM, 0x0002);
1227 	CSR_WRITE_2(sc, VTE_MACSM, 0);
1236 		CSR_WRITE_2(sc, VTE_MDCSC, mdcsc);
1285 	CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);
1286 	CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);
1287 	CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);
1292 	CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);
1293 	CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);
1298 	CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);
1299 	CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);
1306 	CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |
1319 	CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);
1322 	CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |
1333 	CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);
1340 	CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |
1347 	CSR_WRITE_2(sc, VTE_MRICR, 0);
1348 	CSR_WRITE_2(sc, VTE_MTICR, 0);
1351 	CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);
1356 	CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);
1357 	CSR_WRITE_2(sc, VTE_MISR, 0);
1401 	CSR_WRITE_2(sc, VTE_MIER, 0);
1402 	CSR_WRITE_2(sc, VTE_MECIER, 0);
1456 		CSR_WRITE_2(sc, VTE_MCR0, mcr);
1481 		CSR_WRITE_2(sc, VTE_MCR0, mcr);
1655 	CSR_WRITE_2(sc, VTE_MAR0, mchash[0]);
1656 	CSR_WRITE_2(sc, VTE_MAR1, mchash[1]);
1657 	CSR_WRITE_2(sc, VTE_MAR2, mchash[2]);
1658 	CSR_WRITE_2(sc, VTE_MAR3, mchash[3]);
1662 		CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,
1664 		CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,
1666 		CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,
1670 	CSR_WRITE_2(sc, VTE_MCR0, mcr);
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