Cross Reference: /src/sys/dev/pci/if

Lines Matching defs:pif_wcsr
190 #define PIF_WCSR(csr, val)	pif_wcsr(sc, csr, val)
196 pif_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val)
235 	PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE);
237 	PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE);
317 	PIF_WCSR(SWAPPER_CTRL, val);
318 	PIF_WCSR(SWAPPER_CTRL, val);
337 		PIF_WCSR(GPIO_CONTROL, fix_mac[i]);
344 	PIF_WCSR(SW_RESET, 0xa5a5a50000000000ULL);
355 	PIF_WCSR(SWAPPER_CTRL, val);
356 	PIF_WCSR(SWAPPER_CTRL, val);
373 	PIF_WCSR(SW_RESET, 0);
381 	PIF_WCSR(RMAC_ADDR_CMD_MEM,
398 	PIF_WCSR(TX_FIFO_P0, TX_FIFO_LEN0(NTXDESCS));
399 	PIF_WCSR(TX_FIFO_P1, 0ULL);
400 	PIF_WCSR(TX_FIFO_P2, 0ULL);
401 	PIF_WCSR(TX_FIFO_P3, 0ULL);
408 	PIF_WCSR(TX_FIFO_P0, val);
411 	PIF_WCSR(TX_PA_CFG,
452 	PIF_WCSR(RX_QUEUE_PRIORITY, 0ULL); /* only use one ring */
455 	PIF_WCSR(RX_W_ROUND_ROBIN_0, 0ULL); /* only use one ring */
456 	PIF_WCSR(RX_W_ROUND_ROBIN_1, 0ULL);
457 	PIF_WCSR(RX_W_ROUND_ROBIN_2, 0ULL);
458 	PIF_WCSR(RX_W_ROUND_ROBIN_3, 0ULL);
459 	PIF_WCSR(RX_W_ROUND_ROBIN_4, 0ULL);
462 	PIF_WCSR(PRC_RXD0_0, (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr);
466 	PIF_WCSR(PRC_ALARM_ACTION, 0ULL); /* Default everything to retry */
476 	PIF_WCSR(PRC_CTRL_0, RC_IN_SVC | val);
481 	PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 64)); /* all 64M to queue 0 */
496 	PIF_WCSR(MC_RLDRAM_MRS, val);
503 	PIF_WCSR(TTI_DATA1_MEM, TX_TIMER_VAL(0x1ff) | TX_TIMER_AC |
505 	PIF_WCSR(TTI_DATA2_MEM,
507 	PIF_WCSR(TTI_COMMAND_MEM, TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE);
512 	PIF_WCSR(RTI_DATA1_MEM, RX_TIMER_VAL(0x800) | RX_TIMER_AC |
514 	PIF_WCSR(RTI_DATA2_MEM,
516 	PIF_WCSR(RTI_COMMAND_MEM, RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE);
619 	PIF_WCSR(ADAPTER_CONTROL, val);
624 	PIF_WCSR(ADAPTER_CONTROL, val);
658 	PIF_WCSR(ADAPTER_CONTROL, val);
664 	PIF_WCSR(TX_TRAFFIC_MASK, 0);
665 	PIF_WCSR(RX_TRAFFIC_MASK, 0);
666 	PIF_WCSR(GENERAL_INT_MASK, 0);
667 	PIF_WCSR(TXPIC_INT_MASK, 0);
668 	PIF_WCSR(RXPIC_INT_MASK, 0);
669 	PIF_WCSR(MAC_INT_MASK, MAC_TMAC_INT); /* only from RMAC */
670 	PIF_WCSR(MAC_RMAC_ERR_MASK, ~RMAC_LINK_STATE_CHANGE_INT);
688 	PIF_WCSR(ADAPTER_CONTROL, val);
710 	PIF_WCSR(GENERAL_INT_STATUS, val);
717 		PIF_WCSR(MAC_RMAC_ERR_REG, RMAC_LINK_STATE_CHANGE_INT);
726 		PIF_WCSR(TX_TRAFFIC_INT, val); /* clear interrupt bits */
762 		PIF_WCSR(RX_TRAFFIC_INT, val); /* Clear interrupt bits */
854 			PIF_WCSR(RMAC_MAX_PYLD_LEN,
905 		PIF_WCSR(RMAC_ADDR_DATA0_MEM, val << 16);
906 		PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL);
907 		PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE |
917 		PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0xffffffffffff0000ULL);
918 		PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL);
919 		PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE |
930 	PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0x8000000000000000ULL);
931 	PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xF000000000000000ULL);
932 	PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE |
1233 	PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50);
1234 	PIF_WCSR(DTX_CONTROL, 0x80000515000000E0ULL); DELAY(50);
1235 	PIF_WCSR(DTX_CONTROL, 0x80000515D93500E4ULL); DELAY(50);
1238 	PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50);
1239 	PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50);
1240 	PIF_WCSR(DTX_CONTROL, 0x80010515001e00e4ULL); DELAY(50);
1243 	PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50);
1244 	PIF_WCSR(DTX_CONTROL, 0x80020515000000E0ULL); DELAY(50);
1245 	PIF_WCSR(DTX_CONTROL, 0x80020515F21000E4ULL); DELAY(50);
1248 	PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50);
1249 	PIF_WCSR(DTX_CONTROL, 0x80000515000000e0ULL); DELAY(50);
1250 	PIF_WCSR(DTX_CONTROL, 0x80000515000000ecULL); DELAY(50);
1252 	PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50);
1253 	PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50);
1254 	PIF_WCSR(DTX_CONTROL, 0x80010515000000ecULL); DELAY(50);
1256 	PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50);
1257 	PIF_WCSR(DTX_CONTROL, 0x80020515000000e0ULL); DELAY(50);
1258 	PIF_WCSR(DTX_CONTROL, 0x80020515000000ecULL); DELAY(50);
1262 	PIF_WCSR(DTX_CONTROL, 0x0018040000000000ULL); DELAY(50);
1263 	PIF_WCSR(DTX_CONTROL, 0x00180400000000e0ULL); DELAY(50);
1264 	PIF_WCSR(DTX_CONTROL, 0x00180400000000ecULL); DELAY(50);
1283 	PIF_WCSR(DTX_CONTROL, 0x0000051500000000ULL); DELAY(50);
1284 	PIF_WCSR(DTX_CONTROL, 0x00000515604000e0ULL); DELAY(50);
1285 	PIF_WCSR(DTX_CONTROL, 0x00000515604000e4ULL); DELAY(50);
1286 	PIF_WCSR(DTX_CONTROL, 0x00000515204000e4ULL); DELAY(50);
1287 	PIF_WCSR(DTX_CONTROL, 0x00000515204000ecULL); DELAY(50);
1299 	PIF_WCSR(MDIO_CONTROL, 0x0018040000000000ULL); DELAY(50);
1300 	PIF_WCSR(MDIO_CONTROL, 0x00180400000000e0ULL); DELAY(50);
1301 	PIF_WCSR(MDIO_CONTROL, 0x00180400000000ecULL); DELAY(50);
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