Cross Reference: /src/sys/dev/pci/if

Lines Matching defs:rxd
98 #define rxd_4k CONCAT3(rxd, RX_MODE, _4k)
99 #define rxdesc ___CONCAT(rxd, RX_MODE)
766 		struct rxdesc *rxd;
772 		rxd = XGE_RXD(sc->sc_nextrx);
773 		if (rxd->rxd_control1 & RXD_CTL1_OWN) {
781 		plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2);
785 		plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2);
786 		plen += m->m_next->m_len = RXD_CTL2_BUF1SIZ(rxd->rxd_control2);
788 		    RXD_CTL2_BUF2SIZ(rxd->rxd_control2);
790 		    RXD_CTL3_BUF3SIZ(rxd->rxd_control3);
792 		    RXD_CTL3_BUF4SIZ(rxd->rxd_control3);
797 		val = rxd->rxd_control1;
802 			rxd->rxd_control2 = RXD_MKCTL2(MCLBYTES, 0, 0);
803 			rxd->rxd_control1 = RXD_CTL1_OWN;
1137 	struct rxdesc *rxd;
1147 	rxd = &sc->sc_rxd_4k[page]->r4_rxd[desc];
1205 	rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, 0, 0);
1206 	rxd
1207 	rxd->rxd_control1 = RXD_CTL1_OWN;
1210 	rxd->rxd_control3 = RXD_MKCTL3(0, m[3]->m_len, m[4]->m_len);
1211 	rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, m[1]->m_len, m[2]->m_len);
1212 	rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr;
1213 	rxd->rxd_buf1 = (uint64_t)sc->sc_rxm[id]->dm_segs[1].ds_addr;
1214 	rxd->rxd_buf2 = (uint64_t)sc->sc_rxm[id]->dm_segs[2].ds_addr;
1215 	rxd->rxd_buf3 = (uint64_t)sc->sc_rxm[id]->dm_segs[3].ds_addr;
1216 	rxd->rxd_buf4 = (uint64_t)sc->sc_rxm[id]->dm_segs[4].ds_addr;
1217 	rxd->rxd_control1 = RXD_CTL1_OWN;
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