Lines Matching defs:hw
26 * @hw: pointer to the HW structure
29 igc_init_nvm_params_i225(struct igc_hw *hw)
31 struct igc_nvm_info *nvm = &hw->nvm;
32 uint32_t eecd = IGC_READ_REG(hw, IGC_EECD);
64 if (igc_get_flash_presence_i225(hw)) {
65 hw->nvm.type = igc_nvm_flash_hw;
71 hw->nvm.type = igc_nvm_invm;
82 * @hw: pointer to the HW structure
85 igc_init_mac_params_i225(struct igc_hw *hw)
87 struct igc_mac_info *mac = &hw->mac;
88 struct igc_dev_spec_i225 *dev_spec = &hw->dev_spec._i225;
93 igc_init_mac_ops_generic(hw);
96 hw->phy.media_type = igc_media_type_copper;
104 /* hw initialization */
134 * @hw: pointer to the HW structure
137 igc_init_phy_params_i225(struct igc_hw *hw)
139 struct igc_phy_info *phy = &hw->phy;
144 if (hw->phy.media_type != igc_media_type_copper) {
165 ret_val = hw->phy.ops.reset(hw);
169 ret_val = igc_get_phy_id(hw);
178 * @hw: pointer to the HW structure
183 igc_reset_hw_i225(struct igc_hw *hw)
194 ret_val = igc_disable_pcie_master_generic(hw);
199 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
201 IGC_WRITE_REG(hw, IGC_RCTL, 0);
202 IGC_WRITE_REG(hw, IGC_TCTL, IGC_TCTL_PSP);
203 IGC_WRITE_FLUSH(hw);
207 ctrl = IGC_READ_REG(hw, IGC_CTRL);
210 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_DEV_RST);
212 ret_val = igc_get_auto_rd_done_generic(hw);
223 IGC_WRITE_REG(hw, IGC_IMC, 0xffffffff);
224 IGC_READ_REG(hw, IGC_ICR);
227 ret_val = igc_check_alt_mac_addr_generic(hw);
233 * @hw: pointer to the HW structure
241 igc_acquire_nvm_i225(struct igc_hw *hw)
247 ret_val = igc_acquire_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
253 * @hw: pointer to the HW structure
259 igc_release_nvm_i225(struct igc_hw *hw)
263 igc_release_swfw_sync_i225(hw, IGC_SWFW_EEP_SM);
267 * @hw: pointer to the HW structure
274 igc_acquire_swfw_sync_i225(struct igc_hw *hw, uint16_t mask)
285 if (igc_get_hw_semaphore_i225(hw)) {
290 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);
297 igc_put_hw_semaphore_generic(hw);
309 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);
311 igc_put_hw_semaphore_generic(hw);
318 * @hw: pointer to the HW structure
325 igc_release_swfw_sync_i225(struct igc_hw *hw, uint16_t mask)
331 while (igc_get_hw_semaphore_i225(hw) != IGC_SUCCESS)
334 swfw_sync = IGC_READ_REG(hw, IGC_SW_FW_SYNC);
336 IGC_WRITE_REG(hw, IGC_SW_FW_SYNC, swfw_sync);
338 igc_put_hw_semaphore_generic(hw);
343 * @hw: pointer to the HW structure
350 igc_setup_copper_link_i225(struct igc_hw *hw)
357 ctrl = IGC_READ_REG(hw, IGC_CTRL);
360 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
362 phpm_reg = IGC_READ_REG(hw, IGC_I225_PHPM);
364 IGC_WRITE_REG(hw, IGC_I225_PHPM, phpm_reg);
366 ret_val = igc_setup_copper_link_generic(hw);
372 * @hw: pointer to the HW structure
377 igc_get_hw_semaphore_i225(struct igc_hw *hw)
380 int timeout = hw->nvm.word_size + 1;
387 swsm = IGC_READ_REG(hw, IGC_SWSM);
399 if (hw->dev_spec._i225.clear_semaphore_once) {
400 hw->dev_spec._i225.clear_semaphore_once = false;
401 igc_put_hw_semaphore_generic(hw);
403 swsm = IGC_READ_REG(hw, IGC_SWSM);
421 swsm = IGC_READ_REG(hw, IGC_SWSM);
422 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);
425 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)
433 igc_put_hw_semaphore_generic(hw);
442 * @hw: pointer to the HW structure
451 igc_read_nvm_srrd_i225(struct igc_hw *hw, uint16_t offset, uint16_t words,
466 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
467 status = igc_read_nvm_eerd(hw, offset, count, data + i);
468 hw->nvm.ops.release(hw);
481 * @hw: pointer to the HW structure
496 igc_write_nvm_srwr_i225(struct igc_hw *hw, uint16_t offset, uint16_t words,
511 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
512 status = __igc_write_nvm_srwr(hw, offset, count,
514 hw->nvm.ops.release(hw);
526 * @hw: pointer to the HW structure
537 __igc_write_nvm_srwr(struct igc_hw *hw, uint16_t offset, uint16_t words,
540 struct igc_nvm_info *nvm = &hw->nvm;
561 IGC_WRITE_REG(hw, IGC_SRWR, eewr);
564 if (IGC_NVM_RW_REG_DONE & IGC_READ_REG(hw, IGC_SRWR)) {
582 * @hw: pointer to the HW structure
588 igc_validate_nvm_checksum_i225(struct igc_hw *hw)
595 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
600 read_op_ptr = hw->nvm.ops.read;
601 hw->nvm.ops.read = igc_read_nvm_eerd;
603 status = igc_validate_nvm_checksum_generic(hw);
606 hw->nvm.ops.read = read_op_ptr;
608 hw->nvm.ops.release(hw);
617 * @hw: pointer to the HW structure
624 igc_update_nvm_checksum_i225(struct igc_hw *hw)
636 ret_val = igc_read_nvm_eerd(hw, 0, 1, &nvm_data);
642 if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
643 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
649 ret_val = igc_read_nvm_eerd(hw, i, 1, &nvm_data);
651 hw->nvm.ops.release(hw);
659 ret_val = __igc_write_nvm_srwr(hw, NVM_CHECKSUM_REG, 1,
662 hw->nvm.ops.release(hw);
667 hw->nvm.ops.release(hw);
669 ret_val = igc_update_flash_i225(hw);
678 * @hw: pointer to the HW structure
681 igc_get_flash_presence_i225(struct igc_hw *hw)
688 eec = IGC_READ_REG(hw, IGC_EECD);
699 * @hw: pointer to the HW structure
703 igc_set_flsw_flash_burst_counter_i225(struct igc_hw *hw, uint32_t burst_counter)
712 IGC_WRITE_REG(hw, IGC_I225_FLSWCNT, burst_counter);
724 * @hw: pointer to the HW structure
729 igc_write_erase_flash_command_i225(struct igc_hw *hw, uint32_t opcode,
738 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
744 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
755 IGC_WRITE_REG(hw, IGC_I225_FLSWCTL, flswctl);
758 flswctl = IGC_READ_REG(hw, IGC_I225_FLSWCTL);
773 * @hw: pointer to the HW structure
776 igc_update_flash_i225(struct igc_hw *hw)
787 block_sw_protect = IGC_READ_REG(hw, IGC_I225_FLSECU) &
790 fw_valid_bit = IGC_READ_REG(hw, IGC_FWSM) & IGC_FWSM_FW_VALID_I225;
792 ret_val = igc_pool_flash_update_done_i225(hw);
798 flup = IGC_READ_REG(hw, IGC_EECD) | IGC_EECD_FLUPD_I225;
799 IGC_WRITE_REG(hw, IGC_EECD, flup);
801 ret_val = igc_pool_flash_update_done_i225(hw);
813 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_SEC1VAL_I225)
817 ret_val = igc_write_erase_flash_command_i225(hw,
829 ret_val = igc_set_flsw_flash_burst_counter_i225(hw,
835 ret_val = igc_write_erase_flash_command_i225(hw,
840 ret_val = igc_read_nvm_eerd(hw, current_offset, 1,
848 IGC_WRITE_REG(hw, IGC_I225_FLSWDATA,
853 ret_val = igc_poll_eerd_eewr_done(hw,
866 * @hw: pointer to the HW structure
869 igc_pool_flash_update_done_i225(struct igc_hw *hw)
877 reg = IGC_READ_REG(hw, IGC_EECD);
889 * @hw: pointer to the HW structure
896 igc_set_ltr_i225(struct igc_hw *hw, bool link)
906 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
911 if ((hw->phy.media_type == igc_media_type_copper) &&
912 !(hw->dev_spec._i225.eee_disable) &&
915 ltrc = IGC_READ_REG(hw, IGC_LTRC) | IGC_LTRC_EEEMS_EN;
916 IGC_WRITE_REG(hw, IGC_LTRC, ltrc);
920 tw_system = ((IGC_READ_REG(hw, IGC_EEE_SU) &
924 tw_system = (IGC_READ_REG(hw, IGC_EEE_SU) &
932 size = IGC_READ_REG(hw, IGC_RXPBS) & IGC_RXPBS_SIZE_I225_MASK;
935 if (IGC_READ_REG(hw, IGC_DMACR) & IGC_DMACR_DMAC_EN) {
936 size -= (IGC_READ_REG(hw, IGC_DMACR) &
945 size -= hw->dev_spec._i225.mtu;
970 ltrv = IGC_READ_REG(hw, IGC_LTRMINV);
974 IGC_WRITE_REG(hw, IGC_LTRMINV, ltrv);
977 ltrv = IGC_READ_REG(hw, IGC_LTRMAXV);
981 IGC_WRITE_REG(hw, IGC_LTRMAXV, ltrv);
989 * @hw: pointer to the HW structure
996 igc_check_for_link_i225(struct igc_hw *hw)
998 struct igc_mac_info *mac = &hw->mac;
1018 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
1029 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
1041 igc_check_downshift_generic(hw);
1053 mac->ops.config_collision_dist(hw);
1060 ret_val = igc_config_fc_after_link_up_generic(hw);
1067 ret_val = igc_set_ltr_i225(hw, link);
1073 * @hw: pointer to the HW structure
1078 igc_init_function_pointers_i225(struct igc_hw *hw)
1080 igc_init_mac_ops_generic(hw);
1081 igc_init_phy_ops_generic(hw);
1082 igc_init_nvm_ops_generic(hw);
1083 hw->mac.ops.init_params = igc_init_mac_params_i225;
1084 hw->nvm.ops.init_params = igc_init_nvm_params_i225;
1085 hw->phy.ops.init_params = igc_init_phy_params_i225;
1088 /* igc_init_hw_i225 - Init hw for I225
1089 * @hw: pointer to the HW structure
1091 * Called to initialize hw for i225 hw family.
1094 igc_init_hw_i225(struct igc_hw *hw)
1100 ret_val = igc_init_hw_base(hw);
1106 * @hw: pointer to the HW structure
1115 igc_set_eee_i225(struct igc_hw *hw, bool adv2p5G, bool adv1G,
1122 if (hw->mac.type != igc_i225 ||
1123 hw->phy.media_type != igc_media_type_copper)
1125 ipcnfg = IGC_READ_REG(hw, IGC_IPCNFG);
1126 eeer = IGC_READ_REG(hw, IGC_EEER);
1129 if (!(hw->dev_spec._i225.eee_disable)) {
1130 uint32_t eee_su = IGC_READ_REG(hw, IGC_EEE_SU);
1159 IGC_WRITE_REG(hw, IGC_IPCNFG, ipcnfg);
1160 IGC_WRITE_REG(hw, IGC_EEER, eeer);
1161 IGC_READ_REG(hw, IGC_IPCNFG);
1162 IGC_READ_REG(hw, IGC_EEER);