Cross Reference: /src/sys/dev/pci/igc/igc

Lines Matching defs:nvm
31 	struct igc_nvm_info *nvm = &hw->nvm;
51 	nvm->word_size = 1 << size;
52 	nvm->opcode_bits = 8;
53 	nvm->delay_usec = 1;
54 	nvm->type = igc_nvm_eeprom_spi;
56 	nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8;
57 	nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ? 16 : 8;
59 	if (nvm->word_size == (1 << 15))
60 		nvm->page_size = 128;
62 	nvm->ops.acquire = igc_acquire_nvm_i225;
63 	nvm->ops.release = igc_release_nvm_i225;
65 		hw->nvm.type = igc_nvm_flash_hw;
66 		nvm->ops.read = igc_read_nvm_srrd_i225;
67 		nvm->ops.write = igc_write_nvm_srwr_i225;
68 		nvm->ops.validate = igc_validate_nvm_checksum_i225;
69 		nvm->ops.update = igc_update_nvm_checksum_i225;
71 		hw->nvm.type = igc_nvm_invm;
72 		nvm->ops.write = igc_null_write_nvm;
73 		nvm->ops.validate = igc_null_ops_generic;
74 		nvm->ops.update = igc_null_ops_generic;
380 	int timeout = hw->nvm.word_size + 1;
466 		if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
468 			hw->nvm.ops.release(hw);
511 		if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
514 			hw->nvm.ops.release(hw);
540 	struct igc_nvm_info *nvm = &hw->nvm;
550 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
552 		DEBUGOUT("nvm parameter(s) out of bounds\n");
595 	if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
600 		read_op_ptr = hw->nvm.ops.read;
601 		hw->nvm.ops.read = igc_read_nvm_eerd;
606 		hw->nvm.ops.read = read_op_ptr;
608 		hw->nvm.ops.release(hw);
642 	if (hw->nvm.ops.acquire(hw) == IGC_SUCCESS) {
643 		/* Do not use hw->nvm.ops.write, hw->nvm.ops.read
651 				hw->nvm.ops.release(hw);
662 			hw->nvm.ops.release(hw);
667 		hw->nvm.ops.release(hw);
1084 	hw->nvm.ops.init_params = igc_init_nvm_params_i225;