17  *  @hw: pointer to the HW structure
22 igc_init_mac_ops_generic(struct igc_hw *hw)
24 	struct igc_mac_info *mac = &hw->mac;
35  *  @hw: pointer to the HW structure
38 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG *hw)
46  *  @hw: pointer to the HW structure
54 igc_write_vfta_generic(struct igc_hw *hw, uint32_t offset, uint32_t value)
58 	IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value);
59 	IGC_WRITE_FLUSH(hw);
64  *  @hw: pointer to the HW structure
72 igc_init_rx_addrs_generic(struct igc_hw *hw, uint16_t rar_count)
82 	hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
87 		hw->mac.ops.rar_set(hw, mac_addr, i);
92  *  @hw: pointer to the HW structure
103 igc_check_alt_mac_addr_generic(struct igc_hw *hw)
112 	ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
116 	ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
128 	if (hw->bus.func == IGC_FUNC_1)
132 		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
152 	hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
159  *  @hw: pointer to the HW structure
167 igc_rar_set_generic(struct igc_hw *hw, uint8_t *addr, uint32_t index)
189 	IGC_WRITE_REG(hw, IGC_RAL(index), rar_low);
190 	IGC_WRITE_FLUSH(hw);
191 	IGC_WRITE_REG(hw, IGC_RAH(index), rar_high);
192 	IGC_WRITE_FLUSH(hw);
199  *  @hw: pointer to the HW structure
206 igc_hash_mc_addr_generic(struct igc_hw *hw, uint8_t *mc_addr)
214 	hash_mask = (hw->mac.mta_reg_count * 32) - 1;
247 	switch (hw->mac.mc_filter_type) {
270  *  @hw: pointer to the HW structure
278 igc_update_mc_addr_list_generic(struct igc_hw *hw, uint8_t *mc_addr_list,
287 	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
291 		hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list);
293 		hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
296 		hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
301 	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
302 		IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]);
303 	IGC_WRITE_FLUSH(hw);
308  *  @hw: pointer to the HW structure
313 igc_clear_hw_cntrs_base_generic(struct igc_hw *hw)
317 	IGC_READ_REG(hw, IGC_CRCERRS);
318 	IGC_READ_REG(hw, IGC_ALGNERRC);
319 	IGC_READ_REG(hw, IGC_MPC);
320 	IGC_READ_REG(hw, IGC_SCC);
321 	IGC_READ_REG(hw, IGC_ECOL);
322 	IGC_READ_REG(hw, IGC_MCC);
323 	IGC_READ_REG(hw, IGC_LATECOL);
324 	IGC_READ_REG(hw, IGC_COLC);
325 	IGC_READ_REG(hw, IGC_RERC);
326 	IGC_READ_REG(hw, IGC_DC);
327 	IGC_READ_REG(hw, IGC_TNCRS);
328 	IGC_READ_REG(hw, IGC_HTDPMC);
329 	IGC_READ_REG(hw, IGC_RLEC);
330 	IGC_READ_REG(hw, IGC_XONRXC);
331 	IGC_READ_REG(hw, IGC_XONTXC);
332 	IGC_READ_REG(hw, IGC_XOFFRXC);
333 	IGC_READ_REG(hw, IGC_XOFFTXC);
334 	IGC_READ_REG(hw, IGC_FCRUC);
335 	IGC_READ_REG(hw, IGC_PRC64);
336 	IGC_READ_REG(hw, IGC_PRC127);
337 	IGC_READ_REG(hw, IGC_PRC255);
338 	IGC_READ_REG(hw, IGC_PRC511);
339 	IGC_READ_REG(hw, IGC_PRC1023);
340 	IGC_READ_REG(hw, IGC_PRC1522);
341 	IGC_READ_REG(hw, IGC_GPRC);
342 	IGC_READ_REG(hw, IGC_BPRC);
343 	IGC_READ_REG(hw, IGC_MPRC);
344 	IGC_READ_REG(hw, IGC_GPTC);
345 	IGC_READ_REG(hw, IGC_GORCL);
346 	IGC_READ_REG(hw, IGC_GORCH);
347 	IGC_READ_REG(hw, IGC_GOTCL);
348 	IGC_READ_REG(hw, IGC_GOTCH);
349 	IGC_READ_REG(hw, IGC_RNBC);
350 	IGC_READ_REG(hw, IGC_RUC);
351 	IGC_READ_REG(hw, IGC_RFC);
352 	IGC_READ_REG(hw, IGC_ROC);
353 	IGC_READ_REG(hw, IGC_RJC);
354 	IGC_READ_REG(hw, IGC_MGTPRC);
355 	IGC_READ_REG(hw, IGC_MGTPDC);
356 	IGC_READ_REG(hw, IGC_MGTPTC);
357 	IGC_READ_REG(hw, IGC_TORL);
358 	IGC_READ_REG(hw, IGC_TORH);
359 	IGC_READ_REG(hw, IGC_TOTL);
360 	IGC_READ_REG(hw, IGC_TOTH);
361 	IGC_READ_REG(hw, IGC_TPR);
362 	IGC_READ_REG(hw, IGC_TPT);
363 	IGC_READ_REG(hw, IGC_PTC64);
364 	IGC_READ_REG(hw, IGC_PTC127);
365 	IGC_READ_REG(hw, IGC_PTC255);
366 	IGC_READ_REG(hw, IGC_PTC511);
367 	IGC_READ_REG(hw, IGC_PTC1023);
368 	IGC_READ_REG(hw, IGC_PTC1522);
369 	IGC_READ_REG(hw, IGC_MPTC);
370 	IGC_READ_REG(hw, IGC_BPTC);
371 	IGC_READ_REG(hw, IGC_TSCTC);
372 	IGC_READ_REG(hw, IGC_IAC);
373 	IGC_READ_REG(hw, IGC_RXDMTC);
374 	IGC_READ_REG(hw, IGC_HGORCL);
375 	IGC_READ_REG(hw, IGC_HGORCH);
376 	IGC_READ_REG(hw, IGC_HGOTCL);
377 	IGC_READ_REG(hw, IGC_HGOTCH);
378 	IGC_READ_REG(hw, IGC_LENERRS);
379 	IGC_READ_REG(hw, IGC_TLPIC);
380 	IGC_READ_REG(hw, IGC_RLPIC);
385  *  @hw: pointer to the HW structure
394 igc_setup_link_generic(struct igc_hw *hw)
403 	if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
409 	if (hw->fc.requested_mode == igc_fc_default) {
410 		hw->fc.requested_mode = igc_fc_full;
416 	hw->fc.current_mode = hw->fc.requested_mode;
419 	    hw->fc.current_mode);
422 	ret_val = hw->mac.ops.setup_physical_interface(hw);
431 	IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE);
432 	IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
433 	IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
435 	IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time);
437 	return igc_set_fc_watermarks_generic(hw);
442  *  @hw: pointer to the HW structure
448 igc_config_collision_dist_generic(struct igc_hw *hw)
454 	tctl = IGC_READ_REG(hw, IGC_TCTL);
459 	IGC_WRITE_REG(hw, IGC_TCTL, tctl);
460 	IGC_WRITE_FLUSH(hw);
465  *  @hw: pointer to the HW structure
472 igc_set_fc_watermarks_generic(struct igc_hw *hw)
484 	if (hw->fc.current_mode & igc_fc_tx_pause) {
489 		fcrtl = hw->fc.low_water;
490 		if (hw->fc.send_xon)
493 		fcrth = hw->fc.high_water;
495 	IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl);
496 	IGC_WRITE_REG(hw, IGC_FCRTH, fcrth);
503  *  @hw: pointer to the HW structure
512 igc_force_mac_fc_generic(struct igc_hw *hw)
518 	ctrl = IGC_READ_REG(hw, IGC_CTRL);
526 	 * according to the "hw->fc.current_mode" parameter.
537 	DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
539 	switch (hw->fc.current_mode) {
559 	IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
566  *  @hw: pointer to the HW structure
575 igc_config_fc_after_link_up_generic(struct igc_hw *hw)
577 	struct igc_mac_info *mac = &hw->mac;
599 		ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &mii_status_reg);
602 		ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &mii_status_reg);
615 		ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
619 		ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
665 			if (hw->fc.requested_mode == igc_fc_full)
666 				hw->fc.current_mode = igc_fc_full;
668 				hw->fc.current_mode = igc_fc_rx_pause;
681 				hw->fc.current_mode = igc_fc_tx_pause;
694 				hw->fc.current_mode = igc_fc_rx_pause;
699 			hw->fc.current_mode = igc_fc_none;
707 		ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
714 			hw->fc.current_mode = igc_fc_none;
719 		ret_val = igc_force_mac_fc_generic(hw);
731  *  @hw: pointer to the HW structure
739 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, uint16_t *speed,
746 	status = IGC_READ_REG(hw, IGC_STATUS);
752 		if ((hw->mac.type == igc_i225) &&
781  *  @hw: pointer to the HW structure
786 igc_put_hw_semaphore_generic(struct igc_hw *hw)
792 	swsm = IGC_READ_REG(hw, IGC_SWSM);
795 	IGC_WRITE_REG(hw, IGC_SWSM, swsm);
800  *  @hw: pointer to the HW structure
805 igc_get_auto_rd_done_generic(struct igc_hw *hw)
812 		if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD)
828  *  @hw: pointer to the HW structure
838 igc_disable_pcie_master_generic(struct igc_hw *hw)
845 	ctrl = IGC_READ_REG(hw, IGC_CTRL);
847 	IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
850 		if (!(IGC_READ_REG(hw, IGC_STATUS) &

Indexes created Mon Nov 10 17:20:41 GMT 2025