Cross Reference: /src/sys/dev/pci/igc/igc

Lines Matching refs:phy
24 	struct igc_phy_info *phy = &hw->phy;
28 	phy->ops.init_params = igc_null_ops_generic;
29 	phy->ops.acquire = igc_null_ops_generic;
30 	phy->ops.check_reset_block = igc_null_ops_generic;
31 	phy->ops.force_speed_duplex = igc_null_ops_generic;
32 	phy->ops.get_info = igc_null_ops_generic;
33 	phy->ops.set_page = igc_null_set_page;
34 	phy->ops.read_reg = igc_null_read_reg;
35 	phy->ops.read_reg_locked = igc_null_read_reg;
36 	phy->ops.read_reg_page = igc_null_read_reg;
37 	phy->ops.release = igc_null_phy_generic;
38 	phy->ops.reset = igc_null_ops_generic;
39 	phy->ops.set_d0_lplu_state = igc_null_lplu_state;
40 	phy->ops.set_d3_lplu_state = igc_null_lplu_state;
41 	phy->ops.write_reg = igc_null_write_reg;
42 	phy->ops.write_reg_locked = igc_null_write_reg;
43 	phy->ops.write_reg_page = igc_null_write_reg;
44 	phy->ops.power_up = igc_null_phy_generic;
45 	phy->ops.power_down = igc_null_phy_generic;
142 	struct igc_phy_info *phy = &hw->phy;
148 	if (!phy->ops.read_reg)
151 	ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
155 	phy->id = (uint32_t)(phy_id << 16);
157 	ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
161 	phy->id |= (uint32_t)(phy_id & PHY_REVISION_MASK);
162 	phy->revision = (uint32_t)(phy_id & ~PHY_REVISION_MASK);
179 	struct igc_phy_info *phy = &hw->phy;
194 	    (phy->addr << IGC_MDIC_PHY_SHIFT) | (IGC_MDIC_OP_READ));
237 	struct igc_phy_info *phy = &hw->phy;
252 	    (phy->addr << IGC_MDIC_PHY_SHIFT) | (IGC_MDIC_OP_WRITE));
292 	struct igc_phy_info *phy = &hw->phy;
300 	phy->autoneg_advertised &= phy->autoneg_mask;
303 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
307 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
309 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
315 	if (phy->autoneg_mask & ADVERTISE_2500_FULL) {
317 		ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
339 	DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
342 	if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
348 	if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
354 	if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
360 	if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
366 	if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
370 	if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
376 	if (phy->autoneg_advertised & ADVERTISE_2500_HALF)
380 	if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {
440 	ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
446 	if (phy->autoneg_mask & ADVERTISE_1000_FULL)
447 		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
450 	if (phy->autoneg_mask & ADVERTISE_2500_FULL)
451 		ret_val = phy->ops.write_reg(hw,
470 	struct igc_phy_info *phy = &hw->phy;
479 	phy->autoneg_advertised &= phy->autoneg_mask;
484 	if (!phy->autoneg_advertised)
485 		phy->autoneg_advertised = phy->autoneg_mask;
498 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
503 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
510 	if (phy->autoneg_wait_to_complete) {
550 		ret_val = hw->phy.ops.force_speed_duplex(hw);
586 	struct igc_phy_info *phy = &hw->phy;
591 	switch (phy->type) {
595 		phy->speed_downgraded = false;
617 	if (!hw->phy.ops.read_reg)
622 		ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status);
625 		ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status);
657 	if (!hw->phy.ops.read_reg)
665 		ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status);
676 		ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status);
704 	struct igc_phy_info *phy = &hw->phy;
710 	if (phy->ops.check_reset_block) {
711 		ret_val = phy->ops.check_reset_block(hw);
716 	ret_val = phy->ops.acquire(hw);
726 	DELAY(phy->reset_delay_us);
740 		DEBUGOUT("Timeout expired after a phy reset\n");
742 	phy->ops.release(hw);
761 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
763 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
781 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
783 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
807 		ret_val = hw->phy.ops.acquire(hw);
813 		hw->phy.ops.release(hw);
843 		ret_val = hw->phy.ops.acquire(hw);
849 		hw->phy.ops.release(hw);
874 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
878 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
882 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
888 		ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
890 		ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
895 	ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);