Lines Matching refs:hw
17 * @hw: pointer to the HW structure
22 igc_init_phy_ops_generic(struct igc_hw *hw)
24 struct igc_phy_info *phy = &hw->phy;
50 * @hw: pointer to the HW structure
54 igc_null_set_page(struct igc_hw IGC_UNUSEDARG *hw, uint16_t IGC_UNUSEDARG data)
62 * @hw: pointer to the HW structure
67 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG *hw,
76 * @hw: pointer to the HW structure
79 igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG *hw)
87 * @hw: pointer to the HW structure
91 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG *hw, bool IGC_UNUSEDARG active)
99 * @hw: pointer to the HW structure
104 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG *hw,
113 * @hw: pointer to the HW structure
120 igc_check_reset_block_generic(struct igc_hw *hw)
126 manc = IGC_READ_REG(hw, IGC_MANC);
134 * @hw: pointer to the HW structure
140 igc_get_phy_id(struct igc_hw *hw)
142 struct igc_phy_info *phy = &hw->phy;
151 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
157 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
169 * @hw: pointer to the HW structure
177 igc_read_phy_reg_mdic(struct igc_hw *hw, uint32_t offset, uint16_t *data)
179 struct igc_phy_info *phy = &hw->phy;
196 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
204 mdic = IGC_READ_REG(hw, IGC_MDIC);
228 * @hw: pointer to the HW structure
235 igc_write_phy_reg_mdic(struct igc_hw *hw, uint32_t offset, uint16_t data)
237 struct igc_phy_info *phy = &hw->phy;
254 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
262 mdic = IGC_READ_REG(hw, IGC_MDIC);
282 * @hw: pointer to the HW structure
290 igc_phy_setup_autoneg(struct igc_hw *hw)
292 struct igc_phy_info *phy = &hw->phy;
303 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
309 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
317 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
403 switch (hw->fc.current_mode) {
418 * hw's ability to send PAUSE frames.
440 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
447 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
451 ret_val = phy->ops.write_reg(hw,
460 * @hw: pointer to the HW structure
468 igc_copper_link_autoneg(struct igc_hw *hw)
470 struct igc_phy_info *phy = &hw->phy;
488 ret_val = igc_phy_setup_autoneg(hw);
498 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
503 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
511 ret_val = igc_wait_autoneg(hw);
516 hw->mac.get_link_status = true;
523 * @hw: pointer to the HW structure
531 igc_setup_copper_link_generic(struct igc_hw *hw)
538 if (hw->mac.autoneg) {
542 ret_val = igc_copper_link_autoneg(hw);
550 ret_val = hw->phy.ops.force_speed_duplex(hw);
560 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
567 hw->mac.ops.config_collision_dist(hw);
568 ret_val = igc_config_fc_after_link_up_generic(hw);
577 * @hw: pointer to the HW structure
584 igc_check_downshift_generic(struct igc_hw *hw)
586 struct igc_phy_info *phy = &hw->phy;
604 * @hw: pointer to the HW structure
610 igc_wait_autoneg(struct igc_hw *hw)
617 if (!hw->phy.ops.read_reg)
622 ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status);
625 ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status);
641 * @hw: pointer to the HW structure
649 igc_phy_has_link_generic(struct igc_hw *hw, uint32_t iterations,
657 if (!hw->phy.ops.read_reg)
665 ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status);
676 ret_val = hw->phy.ops.read_reg(hw, MII_BMSR, &phy_status);
694 * @hw: pointer to the HW structure
702 igc_phy_hw_reset_generic(struct igc_hw *hw)
704 struct igc_phy_info *phy = &hw->phy;
711 ret_val = phy->ops.check_reset_block(hw);
716 ret_val = phy->ops.acquire(hw);
720 phpm = IGC_READ_REG(hw, IGC_I225_PHPM);
722 ctrl = IGC_READ_REG(hw, IGC_CTRL);
723 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);
724 IGC_WRITE_FLUSH(hw);
728 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
729 IGC_WRITE_FLUSH(hw);
734 phpm = IGC_READ_REG(hw, IGC_I225_PHPM);
742 phy->ops.release(hw);
749 * @hw: pointer to the HW structure
756 igc_power_up_phy_copper(struct igc_hw *hw)
761 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
763 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
769 * @hw: pointer to the HW structure
776 igc_power_down_phy_copper(struct igc_hw *hw)
781 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
783 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
789 * @hw: pointer to the HW structure
797 igc_write_phy_reg_gpy(struct igc_hw *hw, uint32_t offset, uint16_t data)
807 ret_val = hw->phy.ops.acquire(hw);
810 ret_val = igc_write_phy_reg_mdic(hw, offset, data);
813 hw->phy.ops.release(hw);
815 ret_val = igc_write_xmdio_reg(hw, (uint16_t)offset, dev_addr,
824 * @hw: pointer to the HW structure
833 igc_read_phy_reg_gpy(struct igc_hw *hw, uint32_t offset, uint16_t *data)
843 ret_val = hw->phy.ops.acquire(hw);
846 ret_val = igc_read_phy_reg_mdic(hw, offset, data);
849 hw->phy.ops.release(hw);
851 ret_val = igc_read_xmdio_reg(hw, (uint16_t)offset, dev_addr,
860 * @hw: pointer to the HW structure
867 __igc_access_xmdio_reg(struct igc_hw *hw, uint16_t address, uint8_t dev_addr,
874 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
878 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
882 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
888 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
890 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
895 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
904 * @hw: pointer to the HW structure
910 igc_read_xmdio_reg(struct igc_hw *hw, uint16_t addr, uint8_t dev_addr,
915 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);
920 * @hw: pointer to the HW structure
926 igc_write_xmdio_reg(struct igc_hw *hw, uint16_t addr, uint8_t dev_addr,
931 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data, false);
Indexes created Wed Oct 22 00:09:40 GMT 2025